VG-SOT MRAM Design and Performance Analysis

Abstract

Voltage-Gated Spin-Orbit Torque (VG-SOT) Magnetic Tunneling Junction (MTJ) device has the aptitude for acquiring non-volatile memories (NVM), logic cells, neuromorphic circuits featuring low power, high-speed, and high-density. The characteristics of simultaneous field-free SOT switching and Voltage-Controlled Magnetic Anisotropy (VCMA) effect that modulates the barrier energy of the MTJ make it prominent among other MTJ devices. The VG-SOT MTJ device has separate read-write paths requiring two transistors and a diode per bit-cell to control read-write operation properly. This paper proposes a 2-Transistor, 1-Diode, 1-MTJ (2T1D1MTJ) VG-SOT Magnetic Random-Access Memory (MRAM) design. This design achieved an average write power of 10 µW, an average read power of 1.142 µW, and a read-write frequency of 250 MHz. In this design, a commercial 22 nm Fully Depleted Silicon on Insulator (FDSOI) Process Design Kit (PDK), a physics-based VG-SOT MTJ device model developed by Spinlib, and Cadence Spectre simulator has been used to evaluate functionality and performance.