Gate Complementary Metal Oxide Semiconductor Research Articles

Novel High-Performance Analog Devices for Advanced Low-Power High-k Metal Gate Complementary Metal–Oxide–Semiconductor Technology

High performance analog (HPA) devices in high-k metal gate (HKMG) scheme with innovative halo engineering have been successfully demonstrated to produce superior analog and digital performance for low power applications. HPA device was processed “freely” with no extra mask, no extra litho, and no extra process step. This paper details a comprehensive study of the analog and digital characteristics of these HPA devices in comparison with analog control (conventional digital devices with matched geometry). Analog properties such as output voltage gain (also called self-gain), trans-conductance Gm, conductance Gds, Gm/Id, mismatching (MM) behavior, flicker noise (1/f noise) and current linearity have clearly reflected the advantage of HPA devices over analog control, while DC performance (e.g., Ion–Ioff, Ioff–Vtsat, DIBL, Cjswg) and reliability (HCI) have also shown the comparability of HPA devices over control.

Novel High-Performance Analog Devices for Advanced Low-Power High-kMetal Gate Complementary Metal–Oxide–Semiconductor Technology

Novel High-Performance Analog Devices for Advanced Low-Power High-<i>k</i>Metal Gate Complementary Metal–Oxide–Semiconductor Technology

Transient Analysis of CMOS-Gate-Driven $RLGC$ Interconnects Based on FDTD

As the feature size of integrated circuits shrinking in deep submicron technologies, time delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate-driven interconnects become critical issues. Traditionally, CMOS driver is simplified as a linear circuit in which a constant resistance is used to approximate the nonlinear and time-varying MOS resistance, which is inaccurate for signal integrity analysis in high-speed interconnect systems. This paper proposes a finite-difference time-domain (FDTD)-based method for transient analysis of lossy transmission lines in the presence of the nonlinear behavior of CMOS gates. The conventional FDTD with second-order accuracy is used for interconnect analysis and the parameters with frequency-dependent losses are also included. The nonlinear behavior of CMOS gates is represented by alpha-power law model, with the drain current described by piecewise linear function of the drain voltage and discretized in time domain for the FDTD implementation. Explicit forms of the boundary conditions are derived from the implicit interface equations and hence the stability is strictly constrained by Courant condition. Experimental results show that the proposed method has good accuracy and high efficiency with respect to HSPICE. Therefore, it is useful for accurate prediction of time delay and crosstalk noise in high-speed interconnect systems.

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

With the scaling of complementary metal-oxide-semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform.

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

Maximizing performance for higher K gate dielectrics

Further scaling of complementary metal oxide semiconductor gate stacks will require gate dielectrics with a higher dielectric constant (K) than HfO2. We point out that this will require strategies to minimize the overall effective oxide thickness of the gate stack, and not just maximizing the dielectric constant, so that the channel mobility is not impaired and there is still control of the flatband voltages. This may require retention of a SiO2-based interfacial layer, and attention should be paid to the flatband voltages of lanthanide oxides. Phase control of HfO2 and ZrO2 by addition of group IV elements offers simpler advances.

Layout Dependent Induced Leakage and its Prevention with Different Shallow Trench Isolation Schemes in 0.18 µm Dual Gate Complementary Metal Oxide Semiconductor Technology

In this paper, an extreme leakage current at the narrowest isolation space between wide active patterns is found to cause severe yield damage and its mechanism and prevention method is investigated in 0.18 µm node high voltage technology. The narrowest isolation space neighboring to wide isolation space becomes much more narrowed in photoresist (PR) masked silicon (Si) trench etch by the effect of layout dependent Si distortion in wide isolation space. The mechanism of Si profile distortion in the wide isolation space by PR mask Si trench etch is well explained in this paper. Nitride masked Si trench etch as another Si trench etch scheme, so called hard mask scheme, is evaluated and proved to be significantly effective to reduce the leakage and improve the yield dramatically. This paper proposes that layout dependency on process performance and yield should be considered and stringently controlled when process scheme is decided.

High-K dielectrics for the gate stack

This article gives an overview of recent developments in the search for the next-generation dielectric for the complementary metal-oxide semiconductor gate stack. After introducing the main quantities of interest, the paper concentrates on a figure of merit that connects two main properties of the gate stack, namely, the leakage current and the capacitance. This is done for single layers as well as for bilayers consisting of interfacial SiOx and a high-K dielectric. In the case of the bilayers, the impact of the interfacial layer SiOx is enormous, reducing the leakage current by an order of magnitude per monolayer. This extreme dependance makes a good correlation between the leakage and the structural parameters nearly impossible. This is illustrated using numerical examples designed to help the reader evaluate the orders of magnitude involved. The origin of the interfacial layer is traced back by means of thermodynamic considerations. As the estimates put forward in the literature do not correspond to the results observed, a detailed review is made, and additional mechanisms are suggested. By using reasonable values for the Gibbs free energy of an interfacial solid silicon oxide phase it is demonstrated how the reaction equilibria shift. Such an interface phase may fundamentally change the stability criteria of oxides on Si. Furthermore, it can also provide a major source of electronic defects that will affect the device performance. Finally, a second figure of merit is introduced that connects the capacitance with a strongly reduced carrier mobility, which might also be related to the same electronic defects.

Growth of a stacked silicon nitride/silicon oxide dielectric on Si(100)

We have recently developed processes to grow ultrathin amorphous silicon oxide and amorphous silicon nitride layers on clean Si(111) and Si(100) surfaces exploring the self-limiting nature of the direct oxidation of Si with O2, and the self-limiting nature of the direct nitridation of Si with atomic N produced by microwave dissociation of N2, at processing temperatures around 500°C. In some of today’s microprocessor devices mixed dielectric systems are used as complementary metal oxide semiconductor gate dielectrics. We demonstrate the use of our processes to produce such systems in various structures, and with maximum control, by exposing oxide to N, or nitride to O2 at 500°C. In addition we produce a stacked layer, consisting of 7–8Å of SiO2 on top of Si(100), with a layer of varying thickness of Si3N4 grown on top of this structure. The growth of Si3N4 occurs at room temperature in this process. Such structures or thermally postprocessed structures thereof should be further examined as potential stacked gate dielectrics in the next generation of Si-based microelectronics.

Ultra-Shallow Junction Formation by Non-Melt Laser Spike Annealing and its Application to Complementary Metal Oxide Semiconductor Devices in 65-nm Node

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Metal Wet Etch Issues and Effects in Dual Metal Gate Stack Integration

This article discusses metal wet etch issues and their effects on high-/metal films in dual work function metal gate stack integration. A versatile process using metal wet etch has been demonstrated to integrate dual metal gate complementary metal oxide semiconductor (CMOS) devices (Z. B. Zhang et al. , in 2005 Symposia on VLSI Technology and Circuits, Kyoto , Japan, June 14–18 , 2000). Different high-/metal films, combinations of films, etch selectivity, thermal stability, interactions among the films, and finally, surface conditions have made the implementation of metal wet etch challenging. Here, representative results using , , in situ steam generated silicon oxide , , Ta, , , , amorphous silicon (a-Si), and tetraethylorthosilicate in dual metal CMOS processing are presented.

Ultrashallow Junction Formation by Self-Limiting LTP and Its Application to Sub-65-nm Node MOSFETs

We have developed a novel laser thermal process that dramatically enhances laser exposure windows by controlling the heating process in a self-limiting way. Key technology is realized by introducing a new process combination of preamorphization implantation and a heat absorber with a phase switch layer, and by optimizing them. The V/sub th/ rolloffs of MOSFETs formed by this method were remarkably improved compared to those by rapid thermal annealing when offset-spacer and halo-implantation processes were not applied. Its effectiveness was also verified in 50-nm gate complementary metal-oxide semiconductor devices for the first time by confirming that the drain current increased with laser fluence beyond the conventional exposure limit.

Suppression of Boron Penetration from Source/Drain-Extension to Improve Gate Leakage Characteristics and Gate-Oxide Reliability for 65-nm Node CMOS and Beyond

Boron penetration from the poly-silicon gate to the silicon substrate through gate dielectrics is a crucial problem in the dual gate complementary metal-oxide semiconductor (CMOS) process. Therefore, the plasma nitridation technique has been studied well, and it has succeeded to suppress boron penetration. However, boron penetration occurs not only from the doped poly-silicon gate but also from the substrate, and resulting in several degradations of gate-oxide characteristics. On the other hand, the boron concentration of source/drain (S/D) extension has been increasing with gate shrinkage. We found that boron penetration from the S/D extension becomes a crucial problem in gate leakage and gate-oxide integrity, particularly for nanoscale positive-channel MOS (pMOS). In this study, we examined several treatments in detail to suppress boron penetration from the S/D extension, and demonstrated that the plasma nitridation treatment after gate etching is the best solution for 65-nm node CMOS and beyond.

Chemical vapor deposition of ruthenium and ruthenium oxide thin films for advanced complementary metal-oxide semiconductor gate electrode applications

A low-temperature (320–480 °C) metal-organic chemical vapor deposition (MOCVD) process was developed for the growth of ruthenium and ruthenium oxide thin films. The process used bis(ethylcyclopentadienyl)ruthenium [Ru(C5H4C2H5)2] and oxygen as, respectively, the ruthenium and oxygen sources. Systematic investigations of film formation mechanisms and associated rate limiting factors that control the nucleation and growth of the Ru and RuO2 phases led to the demonstration that the MOCVD process can be smoothly and reversibly modified to form either Ru or RuO2 through simple and straightforward modifications to the processing conditions–primarily oxygen flow and substrate temperature. In particular, films grown at low oxygen flows (50 sccm) exhibited a metallic Ru phase at processing temperatures below 480 °C. In contrast, films grown at high oxygen flow (300 sccm) were metallic Ru below 400 °C. Above 400 °C, a phase transition was observed from Ru to RuOx (0 &lt; x &lt; 2.0) to RuO2 as the processing temperature was gradually increased to 480 °C.

Metal gate technology for nanoscale transistors—material selection and process integration issues

Reduction of the gate length and gate dielectric thickness in complementary metal oxide semiconductor (CMOS) transistors for higher performance and circuit density aggravates problems such as poly-silicon (poly-Si) gate depletion, high gate resistance, and dopant penetration from doped poly-Si gate. To alleviate these problems in nanoscale transistors, there is immense interest in the replacement of the conventional poly-Si gate material with metal gate materials. A metal gate material not only eliminates the gate depletion and dopant penetration problems but also greatly reduces the gate sheet resistance. In this paper, we discuss the material requirements for metal gate CMOS technology and the challenges involved in the integration of metal gate electrodes in a nanoscale transistor. Issues addressed include the choice of metal gate materials for conventional bulk and advanced transistor structures, the physics of the metal–dielectric interface, and the process integration of these materials in a CMOS process.

Deposition and characterization of HfO2 high k dielectric films

As the scaling of complementary metal-oxide-semiconductor (CMOS) transistors proceeds, the thickness of the SiO2 gate dielectrics shrinks rapidly and results in higher gate leakage currents. High k dielectric materials are acknowledged to be the possible solutions to this challenge, as their higher k values (e.g., 15–50) raise the physical thickness of the dielectrics that provide similar equivalent thickness of a thinner SiO2 film. In order for the high k materials to be applicable in CMOS devices, there should exist deposition technologies that can deposit highly uniform films over Si wafers with diameters as large as 200 mm. This report discusses the deposition process and the correlation between the growth conditions, structural and dielectric properties of HfO2, which is one of the most promising high k dielectric materials. Judging from the thickness uniformity, surface roughness, k value, and interfacial density of state of the HfO2 films, the metalorganic chemical vapor deposition technique was identified to be suitable for growing HfO2 films targeted at applications as CMOS gate dielectrics.

Stacked Metal Layers as Gates for MOSFET Threshold Voltage Control

AbstractTwo layer metal gate stacks allow the effective work function to be tuned by varying the thickness of the first metal layer. Metal-oxide-semiconductor (MOS) capacitors were fabricated by using two metals of very different work functions on thermal oxide gate dielectric where the bottom layer thickness is varied over a range from 0 to 50nm. Electrical and thermal stability measurements were performed on the Al on TaN metal gate stack. The effective workfunction is seen to shift from the value of one metal to the other rapidly as the thickness of the first metal layer is varied from 0 to approximately 10nm. The flat band voltage (Vfb) transition matches the workfunction difference of the two metals in the stack. The advantage of this approach when applied to metal-oxide-semiconductor-field-effect-transistors (MOSFETs) is that it allows the effective workfunction of the metal stack, and the threshold voltage (Vth) of the device to be fine tuned. It also allows for eventual dual gate complementary MOS (CMOS) device fabrication where two different work function metal stacks are necessary, without processing directly on the gate dielectric. A model is proposed to elucidate the workfunction tuning mechanism.

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-k) gate oxide. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other gate stack scaling concerns like boron penetration and elevated gate resistance. Extensive simulations have shown that the optimal gate work functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-type MOSFETs (p-type MOSFETs). This study summarizes the evaluations of TiN, Ta–Si–N, WN, TaN, TaSi, Ir, and IrO2 as candidate metals for dual-metal gate complementary metal–oxide semiconductor using HfO2 as the gate dielectric. The gate work function was determined by fabricating metal–oxide–semiconductor capacitors with varying dielectric thicknesses and different post-gate anneals. The metal–dielectric compatibility was studied by annealing the gate stacks at different temperatures. The gate stacks were characterized using transmission electron microscopy, secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, and x-ray diffraction. Based on work functions and thermal stability, Ta–Si–N and TaN show the most promise as metal electrodes for HfO2 n-MOSFETs.

Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO/sub 2/ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current.

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.