Gate Complementary Metal Oxide Semiconductor Research Articles

Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum layer

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology using low-resistivity (/spl sim/15 /spl mu//spl Omega/cm), bcc (body-centered-cubic)-phase tantalum metal layer has been developed, featuring low-temperature processing below 550/spl deg/C except for gate oxide formation. It was found for the first time that TaNx works not only as a buffer layer which prevents tantalum metal film and gate oxide film from reacting with each other, but also as a seed layer which helps self-growth of bcc-phase tantalum films by hetero-epitaxy. Furthermore, we have demonstrated that the work function of TaNx gate is close to midgap of silicon, hence similar to titanium nitride (TiNx) gate. We have also demonstrated that MOS capacitors on bulk and fully-depleted silicon-on-insulator (FD-SOI) CMOS with TaNx/bcc-Ta/TaNx stacked metal gate structure have excellent electrical characteristics and that the ring-oscillator fabricated using the stacked metal gate CMOS can be operated successfully with 3.8 nm-thickness gate oxide.

SCALPEL mark detection using Si/SiO[sub 2] and 100 keV backscattered electrons

Scattering with angular limitation in projection electron-beam lithography (SCALPEL) marks for alignment and registration have been fabricated in SiO2 deposited in Si trenches using a process that is similar to that used for shallow trench isolation in complementary metal–oxide–semiconductor (CMOS) integrated circuits. The marks were detected using backscattered electrons in a SCALPEL exposure tool using 100 keV incident electrons. The signal-to-noise from the Si/SiO2 marks is comparable to that measured from Si/WSi2 marks fabricated in CMOS gate material. The Si/SiO2 marks fabricated from this process are a viable option for gate alignment to the thin oxide level and is extensible to circuits with critical dimensions less than 100 nm.

Characteristics of Dual Polymetal (W/WNx/Poly-Si) Gate Complementary Metal Oxide Semiconductor for 0.1 µm Dynamic Random Access Memory Technology

We developed a dual polymetal (W/WNx/poly-Si) gate complementary metal oxide semiconductor (MOS) down to a 0.15 µm gate length. The short-channel effects are effectively suppressed and a saturation current of 300 µA/µm is obtained for nMOS and 110 µA/µm is observed for pMOS at a 0.15 µm gate length. The lower saturation current of pMOS is attributed both to the p+-doped poly gate depletion and to the hole mobility degradation due to the increased vertical electric field in the surface-channel pMOS. Boron penetration is not observed with pure SiO2 gate dielectrics. The gate induced drain leakage current could be markedly reduced by optimizing the well doping below the gate edge.

Short-circuit energy dissipation modeling for submicrometer CMOS gates

A significant part of the energy dissipation in static complementary metal-oxide-semiconductor (CMOS) structures is due to short-circuit currents. In this paper, an accurate analytical model for the CMOS short-circuit energy dissipation is presented. First, the short-circuit energy dissipation of the CMOS inverter is modeled. The derived model is based on analytical expressions of the inverter output waveform which include the influences of both transistor currents and the gate-to-drain coupling capacitance. Also, the effect of the short-circuiting transistor's gate-source capacitance on the short-circuit energy dissipation, is taken into account. The /spl alpha/-power law MOS model that considers the carriers' velocity saturation effect of submicrometer devices is used. Second, the inverter model is extended to static CMOS gates by using reduction techniques of series- and parallel-connected transistors. The results produced by the suggested model for a commercial 0.8-/spl mu/m process, show very good agreement with SPICE simulations.

Application of 4-methyl-1-acetoxycalix[6]arene resist to complementary metal–oxide–semiconductor gate processing

Gate lengths from 10 to 30 nm are beyond the reproducible limits of chemically amplified negative resists. Gate stack etching, the most challenging step, requires a negative, nonmetallic resist capable of withstanding enhanced etching with fluorine plasmas. This paper describes a new negative resist, 4-methyl-1-acetoxycalix[6]arene (MAC) which has demonstrated 10 nm scale resolution and etch resistance matching that of novolaks. Because increased etch resistance is required to allow reasonable resist aspect ratios, this work addresses techniques for increasing the etch resistance of MAC resist. The major disadvantage of MAC is its very low sensitivity; to address this we present a technique for combining the use of UVN with MAC.

Simultaneous Formation of Shallow Junctions and Gate Doping for Dual Gate Structures Using Cobalt Silicone as a Dopant Source

The fabrication of high performance dual gate complementary metal oxide semiconductor (CMOS) devices has been demonstrated by dopant implantation into a self‐aligned layer, followed by a single drive‐in annealing. By the optimization of poly‐crystalline Si (poly‐Si) gate thickness and drive‐in annealing conditions, it was shown that CMOS devices annealed at 900°C with gate poly‐Si of 200 nm thickness gives simultaneous formation of shallow junction and gate doping for both n‐channel MOS and p‐channel MOS with a single drive‐in annealing. CMOS devices fabricated with this technology exhibit good junction characteristics. In particular, there is no degradation from silicidation, implantation‐induced damage, gate dopant depletion, or boron penetration. Also, high reliability of the gate oxide and low sheet resistance of can be obtained. Therefore, it is suggested that simultaneous formation of shallow junction and gate doping using Co silicide as a dopant source is a promising technique for the fabrication of high performance dual gate CMOS devices. © 1999 The Electrochemical Society. All rights reserved.

Dynamic and short-circuit power of CMOS gates driving lossless transmission lines

The dynamic and short-circuit power consumption of a complementary metal-oxide-semiconductor (CMOS) gate driving an inductance-capacitance (LC) transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed-form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented. A closed form solution for the short-circuit power is also presented. These solutions agree with circuit simulations within 11% error for a wide range of transistor widths and line impedances for a 0.25-/spl mu/m CMOS technology. The ratio of the short circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects becomes more significant as compared to a resistance-capacitance (RC)-dominated interconnect line.

Subquarter-micrometer Dual Gate Complementary Metal Oxide Semiconductor Field Effect Transistor with Ultrathin Gate Oxide of 2 nm

The high performance of 0.25 µm dual gate complementary metal oxide semiconductor with an ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic applications. Boron penetration can be effectively suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. It is confirmed that N-channel and P-channel metal oxide semiconductor field effect transistors (MOSFETs) with high current drivability can be realized by the thin gate oxide, although the transconductance is not inversely proportional to the gate oxide thickness due to the increase in the effect of the inversion capacitance and the gate depletion. The inverter delay time with the aluminum interconnect load is markedly improved by the highly drivable MOSFETs with thin gate oxide, especially at low-voltage operation. Furthermore, hot carrier degradation of N-channel MOSFETs can be suppressed by reducing the gate oxide thickness. However, it was found that the hot carrier degradation of P-channel MOSFETs is enhanced in the thin gate oxide region under channel hot hole injection.

Input mapping algorithm for modellingof CMOS circuits

An algorithm for mapping every possible input pattern of a complementary metal oxide semiconductor (CMOS) gate to an equivalent set of normalised inputs (inputs which have the same starting point and transition time) is presented. Such an algorithm is required in order to perform analytical modelling of CMOS gates, and the results obtained are very accurate compared to SPICE simulations.

High Performance 0.2 µm Dual Gate Complementary MOS Technologies by Suppression of Transient-Enhanced-Diffusion using Rapid Thermal Annealing

Rapid thermal annealing (RTA) before the low temperature process is introduced in the 0.2 µm dual gate complementary metal oxide semiconductor (CMOS) process and its effect has been systematically investigated. Channel profiles of boron and phosphorus remain steep by the additional RTA process before gate oxidation, as seen by using secondary ion mass spectrometry and a simulation with the point defect based diffusion model. The most effective temperature to suppress transient-enhanced-diffusion (TED) is 900–1000°C, which can be remarkably suppressed by a 30 s treatment in the case of 900°C RTA. A steep channel profile decreases the threshold voltage and increases the transconductance. Shallow source/drain extension profiles of BF2 and phosphorus can be fabricated by an additional RTA process before sidewall spacer film deposition, which can improve the threshold voltage lowering. Consequently, a high current drivability of a 0.2 µm CMOS has been achieved by the suppression of TED using two additional RTA processes.

Oxide loss at the gate periphery during high density plasma etching

This article describes experimental measurements and computer calculations of the location of microtrenches in the gate oxide at the periphery of a complementary metal-oxide semiconductor gate resulting from a polysilicon gate etch with a low pressure, high density plasma, etch tool. When the oxide is removed at the periphery of a gate with the etch process, it is possible to damage the underlying silicon in the source and drain regions. This damage may not be observable in scanning electron microscope pictures but could still lead to device degradation or failure. To measure the integrity of the oxide at the gate periphery, a modified MOS (MMOS) capacitor test structure was used to measure the electric field breakdown strength of the oxide at the gate periphery. The breakdown voltage can be related to the amount of remaining oxide at the gate periphery. This article describes the use of the MMOS test structure to measure the location of the microtrenches relative to the gate edge in a low pressure, high density plasma, polysilicon gate etch tool.

The Most Essential Factor for High-Speed, Low-Power 0.35 µm Complementary Metal-Oxide-Semiconductor Circuits Fabricated on Separation-by-Implanted-Oxygen (SIMOX) Substrates

We present experimental data concerning the propagation delay time and the power consumption of 0.35 µ m complementary metal-oxide-semiconductor (CMOS) gates (inverter, NAND, NOR) fabricated on the commercial standard high dose separation-by-implanted-oxygen (SIMOX) substrates. Each CMOS gate was composed of the fully depleted (FD) mode N- and P-type metal-oxide-semiconductor (NMOS and PMOS) transistors or the partially depleted (PD) mode ones with no body-contact. On the basis of the experimental data, together with SPICE simulation results, we show that the FD-mode is not the primary factor for high-speed, low-power performances of the CMOS/SIMOX circuits, but the reduced drain parasitic capacitance (both the bottom and the peripheral components) with the thin film silicon-on-insulator (SOI) structure is. Furthermore, we show the significance of the design and control of the transistor threshold voltage and/or the off-state leakage current for high-speed, low-power CMOS/SIMOX circuits.

Novel Low Leakage and Low Resistance Titanium Salicide Technology with Recoil Nitrogen Achieved by Silicidation after Ion Implantation through Contamination-Restrained Oxygen Free LPCVD-Nitride Layer (SICRON)

A novel low leakage and low resistance titanium salicide process named “ silicidation after ion implantation through the contamination- restrained oxygen free LPCVD- nitride layer (SICRON)” has been developed. This novel oxygen free process has been successfully implemented in deep submicron dual gate CMOS (complementary metal oxide semiconductor) development. Junction leakage current for TiSi2-n+/p and -p+/n was reduced to the non-silicidation level. Furthermore, low sheet resistances of n+-and p+-gate electrode were maintained below the 0.2 µm line.

Lithography and fabrication processes for sub-100 nm scale complementary metal–oxide semiconductor

We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon-on-insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal-over-gate structure. Mix-and-match lithography, including the use of electron-beam lithography for all critical levels, x-ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to facilitate the scaling of silicon devices toward their ultimate limits.