Gate Bias Voltage Research Articles

Novel Vertical Fin-Based NiO/β-Ga2O3 Heterojunction Field-Effect Transistor with a Low Ron,sp

In this paper, a novel vertical fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (Fin-HJFET) is proposed and studied by TCAD. Theoretically high conduction band offset () enables Ga2O3 Fin-HJFET to produce electron confinement effect at certain gate bias voltage. According to the simulation results, this effect makes Ga2O3 Fin-HJFET can not only form surface-conducting fin channels that are not available in conventional fin-based junction field-effect transistor (Fin-JFET) but also have a stronger electron accumulation capability than Ga2O3 vertical FinFET due to the deep potential well, which leads to a lower specific on-resistance (). In addition, Ga2O3 Fin-HJFET inherits the advantages of Ga2O3 FinFET as a vertical normally-off device and has a higher breakdown voltage compared to FinFET without field plates due to the protection of the highly doped NiO layer. Particularly, Fin-HJFET with different heterojunction band alignments are also considered and discussed. At last, the parameter influence and future optimization space of this highly promising device are explored, providing guidance for actual device fabrication and future device improvement.

Transport Property of Wrinkled Graphene Nanoribbon Tuned by Spin-Polarized Gate Made of Vanadium-Benzene Nanowire.

A series of four-terminal V7(Bz)8-WGNR devices were established with wrinkled graphene nanoribbon (WGNR) and vanadium-benzene nanowire (V7(Bz)8). The spin-polarized V7(Bz)8 as the gate channel was placed crossing the plane, the concave (endo-positioned) and the convex (endo-positioned) surface of WGNR with different curvatures via Van der Waals interaction. The density functional theory (DFT) and nonequilibrium Green's function (NEGF) methods were adopted to calculate the transport properties of these devices at various bias voltages (VS) and gate voltages (VG), such as the conductance, spin-polarized currents, transmission spectra (TS), local density of states (LDOS), and scattering states. The results indicate that the position of V7(Bz)8 and the bending curvature of WGNR play important roles in tuning the transport properties of these four-terminal devices. A spin-polarized transport property is induced for these four-terminal devices by the spin-polarized nature of V7(Bz)8. Particularly, the down-spin channel disturbs strongly on the source-to-drain conductance of WGNR when V7(Bz)8 is endo-positioned crossing the WGNR. Our findings on the novel property of four-terminal V7(Bz)8-WGNR devices provide useful guidelines for achieving flexible graphene-based electronic nanodevices by attaching other similar multidecker metal-arene nanowires.

Transport Characteristics of Silicon Multi-Quantum-Dot Transistor Analyzed by Means of Experimental Parametrization Based on Single-Hole Tunneling Model.

The transport characteristics of a gate-all-around Si multiple-quantum-dot (QD) transistor were studied by means of experimental parametrization using theoretical models. The device was fabricated by using the e-beam lithographically patterned Si nanowire channel, in which the ultrasmall QDs were self-created along the Si nanowire due to its volumetric undulation. Owing to the large quantum-level spacings of the self-formed ultrasmall QDs, the device clearly exhibited both Coulomb blockade oscillation (CBO) and negative differential conductance (NDC) characteristics at room temperature. Furthermore, it was also observed that both CBO and NDC could evolve along the extended blockade region within wide gate and drain bias voltage ranges. By analyzing the experimental device parameters using the simple theoretical single-hole-tunneling models, the fabricated QD transistor was confirmed as comprising the double-dot system. Consequently, based on the analytical energy-band diagram, we found that the formation of ultrasmall QDs with imbalanced energetic natures (i.e., imbalanced quantum energy states and their imbalanced capacitive-coupling strengths between the two dots) could lead to effective CBO/NDC evolution in wide bias voltage ranges.

Nonequilibrium quantum transport properties of tetragonal zinc chalcogenide monolayers

Tetragonal zinc chalcogenide monolayers (TZCM) are emerging as interesting electronic materials with a direct band gap and relatively high carrier mobility. In this work, we report a theoretical investigation of electronic transport properties and photoelectric response properties of TZCM with gold contacts by density functional theory (DFT) and non-equilibrium Green's function (NEGF) methods. When there is no gate voltage applied, the current increases nonlinearly as bias voltage increases. Among the four proposed devices, the Au(100)/ZnS/Au(100) device has the best electronic transport performance and is most sensitive to the adjustment of bias voltage and gate voltage. The photocurrent calculation results indicate that the low-frequency oscillatory photocurrent of the Au(100)/ZnSe/Au(100) device in the high photon energy region may have potential applications in ultraviolet light-emitting diodes. The Au(100)/Zn2SeS/Au(100) device has more stable photoelectric response and polarization sensitivity than the Au(100)/Zn2SSe/Au(100) device. The Au(100)/TZCM/Au(100) devices exhibit considerable photocurrent and good extinction ratios. This work could pave the way for the future application of TZCM in the field of optoelectronics and so on.

Triple-Mode Reciprocal Doherty Power Amplifier With Multi-Band Operation and Extended High Efficiency Range

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76-1.96 GHz band in Mode I, 1.13-1.20/2.48-2.58 GHz bands in Mode II and 0.7-0.76/2.34-2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0-10.5 dB saturation gain, 44.18-46.86 dBm peak output power and 41.9%-61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than -45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

Investigation of topological regime in Bi2Se3 thin films through low-frequency electric noise

Topological insulators are considered new states of quantum matter that cannot be systematically related to conventional insulators and semiconductors. Among them, Bi2Se3 has attracted an increasing interest due to a simple surface band structure and due to a strong contribution of the surface to transport. While the dc electric transport properties have been extensively studied, intrinsic fluctuations and their effect on the surface conduction have received less attention. In order to better investigate these aspects, a detailed characterization of the low-frequency noise, also known as noise spectroscopy, has been made in Bi2Se3 thin films. The experimental results have been obtained for different samples thickness and geometry, in a temperature range from 300 down to 8 K, and as a function of dc bias current and gate voltage. While the observed spectral noise shows a typical thermal and shot noise part, an unusual reduction of the 1/f noise component is found, especially in the low-temperature region. A correlation of this behavior with structural and dc electric transport investigations suggests that it could be an indication of the occurrence of the topological regime. Flicker noise measurements, therefore, could be considered as a valid alternative technique to standard topological surface state spectroscopy.

Electrically switchable and tunable infrared light modulator based on functional graphene metasurface

Abstract Graphene is emerging as an ideal material for new-generation optoelectronic devices. In this paper, a novel graphene metasurface-based electrically switchable and tunable infrared light modulator has been proposed and theoretically studied. The functional modulator comprises a monolayer graphene sheet sandwiched in a Fabry–Perot (FP) like nanostructure consisting of a metal reflector, a dielectric spacer, and an ellipse patterned anisotropy antenna layer. As a result of the photon localization effect of the guided-mode resonance (GMR) in the FP structure, the graphene electroabsorption can be significantly enhanced to enable a high-performance light modulator. By fine-tuning the Fermi energy (E f) of graphene via controlling its bias-gate voltage, the proposed modulator can switch between a perfect absorber and a reflective polarization converter of high conversion efficiency (i.e., >90%) at 1550 nm. The conversion mechanism and the geometric dependences of the infrared light modulator have been investigated. We further demonstrated the tunability of the highly-efficient polarization converter over a broad spectrum by adjusting the real dispersion of E f. Our design concept provides an effective strategy for customizing novel optoelectronic devices by combining an electrically-tunable 2D material with a functional metasurface.

Design of a Current Sensing System with TIA Gain of 160 dBΩ and Input-Referred Noise of 1.8 pArms for Biosensor.

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pArms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm2, and the power consumption of the current sensing system is 12 mW.

Low-frequency noise in ZrS3 van der Waals semiconductor nanoribbons

We report the results of the investigation of low-frequency electronic noise in ZrS3 van der Waals semiconductor nanoribbons. The test structures were of the back-gated field-effect-transistor type with a normally off n-channel and an on-to-off ratio of up to four orders of magnitude. The current–voltage transfer characteristics revealed significant hysteresis owing to the presence of deep levels. The noise in ZrS3 nanoribbons had spectral density SI ∼ 1/fγ (f is the frequency) with γ = 1.3–1.4 within the whole range of the drain and gate bias voltages. We used light illumination to establish that the noise is due to generation–recombination, owing to the presence of deep levels, and determined the energies of the defects that act as the carrier trapping centers in ZrS3 nanoribbons.

Sensitivity of Al-Doped Zinc-Oxide Extended Gate Field Effect Transistors to Low-Dose X-ray Radiation

Herein, we investigated the applicability of thick film and bulk disk forms of aluminum-doped zinc oxide (AZO) for low-dose X-ray radiation dosimetry using the extended gate field effect transistor (EGFET) configuration. The samples were fabricated using the chemical bath deposition (CBD) technique. A thick film of AZO was deposited on a glass substrate, while the bulk disk form was prepared by pressing the collected powders. The prepared samples were characterized via X-ray diffraction (XRD) and field emission scanning electron microscope (FESEM) to determine the crystallinity and surface morphology. The analyses show that the samples are crystalline and comprise nanosheets of varying sizes. The EGFET devices were exposed to different X-ray radiation doses, then characterized by measuring the I-V characteristics pre- and post-irradiation. The measurements revealed an increase in the values of drain-source currents with radiation doses. To study the detection efficiency of the device, various bias voltages were also tested for the linear and saturation regimes. Performance parameters of the devices, such as sensitivity to X-radiation exposure and different gate bias voltage, were found to depend highly on the device geometry. The bulk disk type appears to be more radiation-sensitive than the AZO thick film. Furthermore, boosting the bias voltage increased the sensitivity of both devices.

Half-Integer Conductance Plateau at the ν=2/3 Fractional Quantum Hall State in a Quantum Point Contact.

The ν=2/3 fractional quantum Hall state is the hole-conjugate state to the primary Laughlin ν=1/3 state. We investigate transmission of edge states through quantum point contacts fabricated on a GaAs/AlGaAs heterostructure designed to have a sharp confining potential. When a small but finite bias is applied, we observe an intermediate conductance plateau with G=0.5(e^{2}/h). This plateau is observed in multiple QPCs, and persists over a significant range of magnetic field, gate voltage, and source-drain bias, making it a robust feature. Using a simple model that considers scattering and equilibration between counterflowing charged edge modes, we find this half-integer quantized plateau to be consistent with full reflection of an inner counterpropagating -1/3 edge mode while the outer integer mode is fully transmitted. In a QPC fabricated on a different heterostructure which has a softer confining potential, we instead observe an intermediate conductance plateau at G=(1/3)(e^{2}/h). These results provide support for a model at ν=2/3 in which the edge transitions from a structure having an inner upstream -1/3 charge mode and outer downstream integer mode to a structure with two downstream 1/3 charge modes when the confining potential is tuned from sharp to soft and disorder prevails.

Aging-robust amplifier composed of p-type low voltage OTFT and organic semiconductor load

This paper proposes an amplifier circuit design suitable for low-voltage organic thin-film transistors (OTFTs). To overcome the issues common to low-voltage OTFTs, such as the yield, degradation, and performance differences between p-type and n-type TFTs, we design the circuit based on an inverter comprising only p-type transistors. The optimal bias voltage for the amplifier stage is provided through a bias circuit. The transistor performance degradation is compensated for by sharing the gate bias voltage (i.e. the main cause of degradation) between the bias and amplifier stages. In addition, an organic semiconductor is used as a passive load of the amplifier to reduce the area and failure probability. Test chip measurements demonstrate that the organic material operates as a resistor. The gain and cut-off frequencies of the proposed amplifier circuit can be adjusted by changing the size of the dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]-thiophene resistor, providing a maximum gain of 27 dB. The proposed circuit can operate continuously for over 100 min without significant characteristic changes. The operation of the bias circuit, when applied to a differential amplifier design, is also verified. The differential amplifier achieves a maximum common-mode rejection ratio of 25 dB.

Transient characteristics simulation of total ionizing dose effect on Si n-metal-oxide-semiconductor field effect transistor under different gate voltage

In this work, we establish a novel numerical model of total ionizing dose effect and use it to simulate the radiation degradation of Si n-metal-oxide-semiconductor field effect transistor (NMOSFET) under different bias voltages. The model is based on the capture/emission process of traps, and is used to simulate the transient characteristics of semiconductor devices under total ionizing dose effect. In the simulation, the changes of trapped holes in Si/SiO<sub>2</sub> interface and gate oxide layer are extracted, and it is found that the number of trapped holes at different positions tends to be saturated with the increase of the total dose. When the radiation bias voltage is positive, the degradation amplitude of the threshold voltage is significantly higher than that when the radiation bias voltage is negative. Whether the gate is applied with positive bias or negative bias during the radiation, the degradation amplitude of the threshold voltage shows a trend of first increasing and then decreasing with the increase of the absolute value of radiation bias voltage. Radiation bias voltage also has a certain effect on the annealing effect after radiation. If a gate bias voltage is applied to the device during the annealing, the electrical characteristics recovery amplitude of the device is lower than that under zero bias voltage.

Assessment of interface trapped charge induced threshold voltage hysteresis effect in gate-all-around TFET

In this work, the impact of trapped charge carriers at the semiconductor-dielectric interface has been analyzed. The trapped charge causes the threshold voltage hysteresis effect during ramp up and ramps down of gate bias voltages. It has been shown that the trapped charge occupancy probability depends on the channel electric field and the bias ramp speed, which directly impacts the trapping and detrapping rate of the charge carrier. The simulation sanity has been verified by calibrating the transfer characteristics with the experimentally published data, where the impact on the threshold voltage has been examined by analyzing the impact of the electric field, trap occupation probabilities, band energy fluctuations, and generation and recombination rates. Our findings reveal that if a ramp timespan of 1 μsec is used for the device, then the threshold voltage hysteresis can be a serious reliability concern compared to 1 psec and 0.5 s ramp timespans of GAATFET devices.

High-performance a-ITZO TFTs with high bias stability enabled by self-aligned passivation using a-GaOx

Maintaining gate bias stability under negative bias stress (NBS) and positive bias stress (PBS) is a long-standing issue in amorphous oxide semiconductor thin-film transistors (TFTs). The passivation of the channel layer is crucial for improving device stability. We show that amorphous gallium oxide, which possesses appropriate energy levels (lower electron affinity and higher ionization potential) for indium–tin–zinc oxide (ITZO) TFTs, can be etched selectively by tetramethyl ammonium hydroxide-containing developers that enable self-alignment passivation, such as easy contact hole formation during the drain and source lithography processes. The self-aligned passivation process led to a-ITZO TFTs with high mobility (>50 cm2 V−1 s−1) and low subthreshold swing (<90 mV/dec). The threshold voltage shifts under NBS and PBS using a bias gate voltage of ±20 V for 1 h were −0.09 and 0.15 V, respectively. This passivation can obviate the need for the conventional CVD-derived passivation process by utilizing the DC sputtering of gallium oxide, which may reduce hydrogen issues.

Temperature-Dependent Dynamic on Resistance in Gamma-Irradiated AlGaN/GaN Power HEMTs

Dynamic RON is a key parameter in terms of device reliability and the efficiency of power-switching converters. In this study, commercial off-the-shelf GaN-on-Si power high-electron-mobility transistors (HEMTs) were irradiated using different regimes of accumulative gamma rays with a 60Co source of photon energy (1.33 MeV), while a base temperature of 53 °C and 133 °C during the irradiation test was applied. This test campaign had the objective of investigating how the combination of gamma irradiation and temperature affects dynamic on-resistance (RON) behaviour. The results indicated that gate voltage bias stress affected the degradation of dynamic on-resistance when irradiation was applied, and that temperature was an accelerating factor in dynamic on-resistance degradation. Finally, we obtained a partial reduction in dynamic RON when a total ionising dose of around 140 krad(SiO2) was applied and the base temperature during the irradiation test was not high.

A 24 GHz CMOS Direct-Conversion RF Receiver with I/Q Mismatch Calibration for Radar Sensor Applications.

A 24 GHz millimeter-wave direct-conversion radio-frequency (RF) receiver with wide-range and precise I/Q mismatch calibration is designed in 65 nm CMOS technology for radar sensor applications. The CMOS RF receiver is based on a quadrature direct-conversion architecture. Analytic relations are derived to clearly exhibit the individual contributions of the I/Q amplitude and phase mismatches to the image-rejection ratio (IRR) degradation, which provides a useful design guide for determining the range and resolution of the I/Q mismatch calibration circuit. The designed CMOS RF receiver comprises a low-noise amplifier, quadrature down-conversion mixer, baseband amplifier, and quadrature LO generator. Controlling the individual gate bias voltages of the switching FETs in the down-conversion mixer having a resistive load is found to induce significant changes at the amplitude and phase of the output signal. In the calibration process, the mixer gate bias tuning is first performed for the amplitude mismatch calibration, and the remaining phase mismatch is then calibrated out by the varactor capacitance tuning at the LO buffer's LC load. Implemented in 65 nm CMOS process, the RF receiver achieves 31.5 dB power gain, -35.2 dBm input-referred 1 dB compression power, and 4.8-7.1 dB noise figure across 22.5-26.1 GHz band, while dissipating 106.2 mA from a 1.2 V supply. The effectiveness of the proposed I/Q mismatch calibration is successfully verified by observing that the amplitude and phase mismatches are improved from 1.0-1.5 dB to 0.02-0.19 dB, and from 10.8-23.8 to 1.1-3.2 degrees, respectively.

Electrically Tuning Interfacial Ion Redistribution for mica/WSe2 Memory Transistor

AbstractMemory device is an important part of electronic equipment. 2D transition metal dichalcogenides that exhibit novel electrical characteristics hold promise in developing new types of memory device. Here, the memory effect in 2D mica/WSe2 heterostructure is investigated. Under applying constant bias voltage and gate voltage, the K+ ions in mica will migrate in the direction of the electric field and be trapped to enable the memory function. The gradient K+ ions work as long‐range scatters to electrostatically dope the WSe2 channel. The shift of the threshold voltage indicates an electrostatic doping concentration up to 2.11 × 1012 cm−2. The operating voltage is as low as 10 V and the on/off ratio is estimated to be 104. To determine the mechanism, the dynamic behavior of the device is discussed and a model is proposed which reveals the correlation between the programming/erasing process and the device performance. Moreover, through defining and studying the effective charge trapping rate, θ, it is found that the trapped charge is proportional to the charge flowing through the channel which means that the device performance can be finely tuned by the programming process.

Highly Directive Graphene Based Hybrid Plasmonic Nanoantenna for Terahertz Applications

To satisfy the necessity for elevated data transmission rates in 5G and beyond networks, terahertz band communication (0.1 - 10 THz) is envisaged as a crucial wireless technology. Two-dimensional graphene nanomaterial is being extensively integrated into the plasmonic antennas as it allows them to resonate in the terahertz wave spectrum. In this paper, a graphene-based hybrid terahertz plasmonic nano-scale antenna has been modelled to acquire a maximum gain and directivity of 8.1 dB and 8.23 dBi, respectively, by varying the conductivity of graphene via gate bias voltage. Moreover, a combination of several tailored radiating layers of silver, SiO2 and graphene sheets is arranged in the proposed nanoantenna in such a way that the return loss (S11) of -26.595 dB and a wider bandwidth of 1241.3 GHz are obtained. It is evident that the proposed graphene-based hybrid plasmonic nanoantenna could be considered as an ideal candidate for terahertz communication owing to its excellent radiation characteristics.

0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers

To meet low power requirements for Internet of Things (IoT) applications, the power dissipation of RF transceivers must be very low. As the Low Noise Amplifier (LNA) is one of the most energy consuming parts of an RF receiver, its power optimization is necessary for modern IoT devices. This work presents a 170 $\mu$W LNA capable of operating at 2.4 GHz when powered by a 0.4 V source. It is based on an inverter-based amplifier with improved gate bias voltage and automatic forward bulk biasing to operate at the moderated channel inversion level. A biasing metric is explored to analyze the best dimensions and bulk bias voltages for the NMOS transistor. Post-layout simulation results shown a 2.8 dB noise and competitive specification values compared to the state-of-the-art low-voltage LNAs.