Abstract
In this work, the impact of trapped charge carriers at the semiconductor-dielectric interface has been analyzed. The trapped charge causes the threshold voltage hysteresis effect during ramp up and ramps down of gate bias voltages. It has been shown that the trapped charge occupancy probability depends on the channel electric field and the bias ramp speed, which directly impacts the trapping and detrapping rate of the charge carrier. The simulation sanity has been verified by calibrating the transfer characteristics with the experimentally published data, where the impact on the threshold voltage has been examined by analyzing the impact of the electric field, trap occupation probabilities, band energy fluctuations, and generation and recombination rates. Our findings reveal that if a ramp timespan of 1 μsec is used for the device, then the threshold voltage hysteresis can be a serious reliability concern compared to 1 psec and 0.5 s ramp timespans of GAATFET devices.
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