GaN Power Research Articles

2.6- and 4-W E-Band GaN Power Amplifiers With a Peak Efficiency of 22% and 15.3%

In this letter, we report two high-power gallium nitride (GaN) power amplifiers (PAs) in the Satcom <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> -band (71–86 GHz) with an output power of 2.6 and 4 W, designed by incorporating an ultralow-loss ON-chip integrated power combiner. The first one is a three-stage four-way combining (unit) PA, and the second one is an eight-way combining balanced PA. The unit PA produces a saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{SAT}}$ </tex-math></inline-formula> ) of 34.2 dBm (2.6 W), a peak power-added-efficiency (PAE) of 22%, and an associated power gain of 16.2 dB at 74 GHz. This performance was partly made possible by the design and optimization of the low-loss integrated power combiner, which minimized the losses in the matching networks. In addition, the balanced PA produces a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{SAT}}$ </tex-math></inline-formula> of 36 dBm (4 W), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {1 dB}}$ </tex-math></inline-formula> of 35.6 dBm (3.63 W), with an associated PAE of 15.3% at 80 GHz. To the best of the authors’ knowledge, this is the highest output power (4 W) and the highest PAE (22%) for a PA > 2.5 W reported in any of the III–V technologies at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$ </tex-math></inline-formula> -band.

A Review of High-Speed GaN Power Modules: State of the Art, Challenges, and Solutions

Wide bandgap (WBG) devices are a desirable choice for high-density energy conversion systems. In high-speed hard-switching applications, voltage overshoot across device terminals, oscillations at gate loop and Electro-magnetic Interference (EMI) becomes harder to mitigate and overall system reliability is reduced. To address the key challenges and harness the benefits offered by these latest generations of devices, improved and advanced packaging structures are required, as packaging technology often has a critical impact on module performance and reliability. This paper summarizes the design procedure for power modules, essential parts, and available materials for the fabrication of a power module package. Moreover, it provides a review of commercially available gallium nitride based high electron mobility transistors (GaN HEMTs) and state-of-the-art module packaging technologies adopted for them with a focus on module layout, module integration trends, and identifying their impacts on the GaN HEMT’s performance. Through this review, the paper also discusses major challenges faced by designers with GaN HEMTs in power electronics applications and their potential solutions, which is critical for the mainstream adoptions of GaN HEMTs and defining the future technology roadmap.

Integrated Common-Mode Filter for GaN Power Module With Improved High-Frequency EMI Performance

While the employment of wide bandgap (WBG) devices in high-frequency and high-voltage applications brings benefits such as reduced system size and improved efficiency, it aggravates the electromagnetic interference (EMI) issue due to fast switching. High-frequency EMI noise suppression relies mainly on the filter design, where the filter's performance is strongly affected by parasitics. Through analyzing the common-mode (CM) equivalent circuit of a half-bridge power module, this letter identifies the key parasitics that dominate the performance of a common-mode filter (CMF) at high frequencies. To minimize the parasitics, the concept of integrating the CMF inside the WBG power module package is developed to improve the noise attenuation. A π-type CMF is integrated with a half-bridge GaN-based power module as a prototype to validate the concept. Experiments are conducted by measuring the CM noise spectrum received by the line impedance stabilization networks (LISNs) from the hard switching of the designed power module under 70 V and 80 kHz. Comparing the measured results of the integrated CMF to the externally-added CMF, up to 50 dBμV more attenuation is achieved by the integrated CMF in the frequency range of 10 MHz to 100 MHz, verifying the theoretical analysis and the established CM equivalent circuit.

GaN power converter and high-side IC substrate issues on Si, p-n junction, or SOI

The lateral GaN power semiconductor technology enables monolithic integration of complete power converter topologies such as half-bridges, multi-phase and multi-level converters. Fabrication on Si substrates enables low-cost and mass production. However, the operation of monolithic GaN power converters on a common conductive silicon (Si) substrate is limited compared to discrete GaN HEMTs, especially at high-voltage operation, due to substrate-biasing effects such as back-gated or trap-related static and dynamic on-resistance increase, and changed effective device capacitances. To circumvent the Si substrate related effects but still using a low-cost large-diameter Si substrate, this paper reviews isolation approaches for GaN ICs such as Si p-n junction isolation or floating Si substrates (GaN-on-Si) and buried oxide isolation using Silicon-on-Insulator substrates (GaN-on-SOI). Published GaN power converter ICs are reviewed. The effect of the isolation approaches on increased output and input transistor capacitances, influencing the switching behavior and switching loss, is calculated and compared for different voltage classes (below 100 V to 600 V-class). Finally, design guidelines for local substrate termination using the Si-based isolation approaches are discussed exemplary for a monolithic half-bridge with driver circuit. Monolithic GaN power converter integration combined with functional integration will result in a new class of advanced power converter ICs, and enable efficient, compact and low-cost power conversion applications.

Ion-implanted triple-zone graded junction termination extension for vertical GaN p-n diodes

We demonstrate an ion-implanted triple-zone junction termination extension (JTE) for vertical GaN p-n diodes. Due to the spatial distribution of fixed charge in the triple-zone JTE structure, the peak electric fields at the contact metal edge and at the edge of the JTE are significantly reduced compared to conventional approaches. The forward and reverse characteristics of diodes with conventional single-zone JTE and the triple-zone JTE explored here have been studied and compared experimentally. GaN p-n diodes fabricated using the triple-zone JTE obtain an experimentally measured maximum breakdown voltage of 1.27 kV, appreciably higher than the 1.01 kV achieved using the single-zone JTE structure. The triple-zone JTE design also provides a wider window for fabrication processing and epitaxial wafer growth to achieve the high breakdown voltage compared to single-zone designs. The triple-zone JTE is promising for cost-effective fabrication of GaN power electronics.

Dynamic on-resistance stability of SiC and GaN power devices during high-frequency (100–300 kHz) hard switching and zero voltage switching operations

To our knowledge, this is the first study to investigate the high-frequency (100–300 kHz) switching stability of SiC power devices at a Vds of 800 V during hard switching (HSW) and zero voltage switching (ZVS) operations. In this study, we proposed a topology for evaluating the switching dependencies (i.e., temperature, frequency, current, and duty cycle) in order to determine their flexibility in identifying circuit-level switching stability. We also evaluated the high-frequency switching stability of GaN power devices for comparison purposes. Overall, the results indicated that compared with GaN power devices, SiC power devices have higher dynamic drain-to-source on-resistance stability during ZVS and HSW high-frequency switching operations.

Threshold Optimized CSWPL Behavioral Model for RF Power Transistors Based on Particle Swarm Algorithm

In this letter, the particle swarm optimization (PSO) is employed to optimize the threshold values of the canonical section-wise piecewise linear (CSWPL) function-based behavioral model of power transistors. The effectiveness of the proposed method is validated through measurements carried out on a 10-W GaN power transistor produced by Wolfspeed. Compared with the existing simultaneous perturbation stochastic approximation (SPSA) method, the developed modeling technique not only provides superior prediction performance across different input power levels but also finds the optimal thresholds much more efficiently.

An Isolated Waveguide Divider for W-Band Power Combined Amplifier

In this study, a compact isolated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E$</tex-math> </inline-formula> -plane waveguide T-junction divider has been proposed for power combination with solid-state amplifiers in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$</tex-math> </inline-formula> -band. The measured passive isolation between the output ports is better than 15 dB, with an average loss of 0.2 dB over the range of 77.5–97 GHz. In addition, the return loss is better than 17 dB at the input port. By using two GaN power amplifiers of about 3 W between back-to-back dividers, the power combined module produces a maximum power output of up to 6.2 W within the band of 81–86 GHz, with an average combination efficiency of 90.6%.

Importance of layer distribution in Ni and Au based ohmic contacts to p-type GaN

In this work, we report on the importance of layer distribution after annealing to form a high quality ohmic contact on p-type GaN, using nickel (Ni) and gold (Au) thin layer association. Both the standard GaN/Ni/Au and its reverse, GaN/Au/Ni on p-type GaN were studied. The Au/Ni stack exhibits the most promising results in this study. While the standard GaN/Ni/Au contact exhibits a quasi-linear current-voltage (I-V) characteristic, its counterpart, GaN/Au/Ni, shows pure ohmic behavior, with a specific contact resistance (ρc) as low as 2.0 × 10−4 Ω.cm2 after rapid thermal annealing (RTA) at 500 °C for 5 min under air ambient, equivalent to the best literature results. X-ray diffraction (XRD) and transmission electron microscopy (TEM) analyses demonstrate the incomplete inversion of layers during annealing leading to a GaN/Ni/Au/NiO stack that explains why GaN/Ni/Au contact shows inferior electrical performance. On the other hand, for the GaN/Au/Ni contact annealed in the same conditions, the excellent results can be attributed to both (i) the presence of the gold layer at the interface with GaN, allowing the formation of gallide solid solution (Ga-Au) and (ii) the formation of NiO directly contacted with the p-GaN. Those two mechanisms are known to lead to the formation of good ohmic contact on p-type GaN. These results demonstrate that although GaN/Ni/Au is a standard contact for p-GaN layers, the opposite stack (GaN/Au/Ni) gives the best Ohmic behavior. This is important for achieving the best performance of GaN power diodes or transistors including a p-gate structure.

Double Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification

Wide Bandgap devices (WBG) have led to an era of high speed and high voltage operations that were not previously achievable with silicon devices. However, packaging of these devices in the power module has been a challenge due to higher switching rates which can cause several amperes of displacement current to flow through the parasitic capacitance of the package thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates unlike the traditional inorganic substrates e.g. DBC and thus a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this paper is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and RMS value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.

A Novel Evaluation Methodology for the Reliability and Lifetime of 200 mm E-Mode GaN-on-Si Power HEMTs

In this paper, a novel evaluation methodology for the reliability and lifetime of E-mode AlGaN/GaN HEMTs has been proposed. A practical example of reliability evaluation is presented for commercial 100V E-mode GaN-on-Si power HEMTs, which are fabricated on an industrial 200mm Si CMOS compatible technology platform. Firstly, wafer-level reliability test (WLRT), Joint Electron Device Engineering Council (JEDEC) qualification and dynamic high temperature operating life (DHTOL) test of 200mm GaN-on-Si power HEMTs for mass production have been carried out. Secondly, the relationships of WLRT with JEDEC and DHTOL have been found, therefore, a fast evaluation method for the reliability of commercial 100V E-mode GaN-on-Si power devices has been established. Finally, DHTOL and switching accelerated lifetime test (SALT) have been carried out to demonstrate the validity of the fast evaluation method. In summary, it is proved that the novel evaluation methodology can better screen the robust GaN power devices, and greatly simplify the reliability testing flow of commercial 200mm GaN-on-Si power devices for mass production.

Radiation damage in GaN/AlGaN and SiC electronic and photonic devices

The wide bandgap semiconductors SiC and GaN are commercialized for power electronics and for visible to UV light-emitting diodes in the case of the GaN/InGaN/AlGaN materials system. For power electronics applications, SiC MOSFETs (metal–oxide–semiconductor field effect transistors) and rectifiers and GaN/AlGaN HEMTs and vertical rectifiers provide more efficient switching at high-power levels than do Si devices and are now being used in electric vehicles and their charging infrastructure. These devices also have applications in more electric aircraft and space missions where high temperatures and extreme environments are involved. In this review, their inherent radiation hardness, defined as the tolerance to total doses, is compared to Si devices. This is higher for the wide bandgap semiconductors, due in part to their larger threshold energies for creating defects (atomic bond strength) and more importantly due to their high rates of defect recombination. However, it is now increasingly recognized that heavy-ion-induced catastrophic single-event burnout in SiC and GaN power devices commonly occurs at voltages ∼50% of the rated values. The onset of ion-induced leakage occurs above critical power dissipation within the epitaxial regions at high linear energy transfer rates and high applied biases. The amount of power dissipated along the ion track determines the extent of the leakage current degradation. The net result is the carriers produced along the ion track undergo impact ionization and thermal runaway. Light-emitting devices do not suffer from this mechanism since they are forward-biased. Strain has also recently been identified as a parameter that affects radiation susceptibility of the wide bandgap devices.

A monolithic GaN driver with a deadtime generator (DTG) for high‐temperature (HT) GaN DC‐DC buck converters

AbstractThis paper presents a monolithic GaN driver with a deadtime generator (DTG) for half‐bridge DC‐DC buck converters. The proposed GaN integrated circuits (ICs) were fabricated in a 3 µm enhancement‐mode GaN MIS‐HEMTs process. The integrated DTG converter can operate at 250°C with a large gate swing of 10 V, and it exhibits a maximum efficiency of 80% at high temperatures, with VIN= 30 V at 100 kHz. The monolithic GaN DTG driver requires one control signal and generates a deadtime of fewer than 0.13 µs at high temperatures up to 250°C. The proposed DTG converter is compared to an integrated GaN converter without DTG (w/o) under various conditions. At high temperatures, the optimized GaN DTG converter shows better performance than the GaN converter w/o at high load currents, in terms of smaller voltage overshoots and better efficiency as well. This work demonstrates a simple GaN deadtime method for high temperature (HT) GaN power converters.

Double-Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification

Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.

Recent Developments and Prospects of Fully Recessed MIS Gate Structures for GaN on Si Power Transistors

For high electron mobility transistors (HEMTs) power transistors based on AlGaN/GaN heterojunction, p-GaN gate has been the gate topology commonly used to deplete the two dimensional electron gas (2-DEG) and achieve a normally-OFF behavior. But fully recessed MIS gate GaN power transistors or MOSc-HEMTs have gained interest as normally-OFF HEMTs thanks to the wider voltage swing and reduced gate leakage current when compared to p-GaN gate HEMTs. However the mandatory AlGaN barrier etching to deplete the 2-DEG combined with the nature of the dielectric/GaN interface generates etching-related defects, traps, and roughness. As a consequence, the threshold voltage (VTH) can be unstable, and the electron mobility is reduced, which presents a challenge for the integration of a fully recessed MIS gate. Recent developments have been studied to solve this challenge. In this paper, we discuss developments in gate recess with low impact etching and atomic layer etching (ALE) alongside surface treatments such as wet cleaning, thermal or plasma treatment, all in the scope of having a surface close to pristine. Finally, different interfacial layers, such as AlN, and alternative dielectrics investigated to optimize the dielectric/GaN interface are presented.

ICeGaNTM technology: The easy-to-use and self-protected GaN power IC

• Three types of integration exist in the market of GaN Power Electronics. • New offering, ICeGaN TM , features an optimal level of integration. • Based on a smart interface for reliable, safe and ease-of-use of the GaN transistor. • ICeGaN can achieve much higher power densities in the system compared to Silicon. • ICeGaN can operate cooler and allow reduced bill of material compared to other GaN. This work provides an overview of the current state of technology in the field of lateral GaN power devices and presents the characteristics of the main commercially available 650V GaN power devices and ICs. A comparison is given, both in terms of key parameters as well as of the availability of complex functionality through integration of additional smart features. The features of our new technology, termed ICeGaN™, are presented in this context, focusing on the benefits that may be derived when ICeGaN™ devices are used in common applications. ICeGaN™ is a new concept of a smart HEMT which offers ease-of-use, sensing and protection functions without sacrificing performance.

A 2–10-GHz Reconfigurable GaN Power Amplifier With Average Power-Added Efficiency of 30% and Output Power of 2 W

In this brief, a 2–10 GHz reconfigurable power amplifier (PA) with power-added efficiency (PAE) of 30% and output power of 2W is proposed using commercial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.25~\mathbf {\mu }\text{m}$ </tex-math></inline-formula> GaN technology. It consists of two-stage amplifier transistors with reconfigurable input, inter-stage and output matching networks. By utilizing the reconfigurable matching networks, the proposed PA circuit divides the frequency band of 2–10 GHz into three continuous sub-frequency bands, and achieves high power added efficiency and gain in each sub-frequency band. As a result, the proposed PA can simultaneously maintain high efficiency and high gain and cover multioctave bandwidth. Moreover, in order to further improve the efficiency, harmonic suppression is used in low-band with open circuit impedance at third harmonic. With these techniques, the proposed PA covers frequency band of 2–10 GHz, delivers an average PAE of 38% at 2–5 GHz, 31% at 5–7 GHz, and 31.5% at 7–10 GHz. Good agreement between simulation and measurement is obtained.

Analysis of Multiple Fin-type Vertical GaN Power Transistors based on Bulk GaN Substrates

In this study, the multiple fin-type vertical GaN power transistor based on the GaN-on-GaN were analyzed using the two-dimensional technical computer-aided design (2-D TCAD) simulations. In the field of the electric vehicle systems requiring a high operation voltage of 1,000 V or more, the power devices have a large device area because of the long distance between the gate region and the drain region. This problem can be addressed by using the fin-type vertical GaN power transistor, which can reduce the device area due to its vertical channel. For the high current performance, the multiple fin-type structure was required. Thus, we investigated characteristics depending on the number of fin (NSUBfin/SUB). By comparing the on-state drain currents (ISUBon/SUB), the breakdown voltages (BV), and the on-resistances (RSUBon/SUB) with different NSUBfin/SUB, this study provides an understanding of the electrical properties of the multiple fin-type vertical GaN power transistor affected by NSUBfin/SUB.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Thermal Analysis of Flip-Chip Bonding Designs for GaN Power HEMTs with an On-Chip Heat-Spreading Layer

In this work, we demonstrated the thermal analysis of different flip-chip bonding designs for high power GaN HEMT developed for power electronics applications, such as power converters or photonic driver applications, with large gate periphery and chip size, as well as an Au metal heat-spreading layer deposited on top of a planarized dielectric/passivation layer above the active region. The Au bump patterns can be designed with high flexibility to provide more efficient heat dissipation from the large GaN HEMT chips to an AlN package substrate heat sink with no constraint in the alignment between the HEMT cells and the thermal conduction bumps. Steady-state thermal simulations were conducted to study the channel temperatures of GaN HEMTs with various Au bump patterns at different levels of current and voltage loadings, and the results were compared with the conventional face-up GaN die bonding on an AlN package substrate. The simulations were started from a single finger isolated HEMT cell and then extended to multiple fingers HEMT cells (total gate width > 40 mm) to investigate the "thermal cross-talk" effect from neighboring devices. Thermal analysis of the GaN HEMT under pulse operation was also performed to better reflect the actual conditions in power conversion or pulsed laser driver applications. Our analysis provides a combinational assessment of power GaN HEMT dies under a working condition (e.g., 1MHz, 25% duty cycle) with different flip chip packaging schemes. The analysis indicated that the channel temperature rise (∆T) of a HEMT cell in operation can be reduced by 44~46% by changing from face-up die bonding to a flip-chip bonding scheme with an optimized bump pattern design.