Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

Abstract

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.