Abstract

Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.

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