Gain Error Research Articles

A Multi-Dimensional Calibration Based on Genetic Algorithm in a 12-Bit 750 MS/s Pipelined ADC.

As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively.

A Wideband Low-Loss CMOS Attenuator With dB-Linear Gain Tuning for W-Band Applications

This paper presents the design of a wideband low-loss attenuator at W band. The reflective-type attenuation topology is employed to reduce loss and provide flat gain response. Optimizations of the switched-resistor-based reflective loads enable simultaneous direct-digital control and dB-linear gain tuning. The proof-of-concept W-band attenuator is implemented in 40-nm CMOS technology. Measurement results prove that the proposed attenuator can cover 15.5 dB gain range with 0.5 dB step and < 0.2 dB RMS gain error over 70–110 GHz band. The insertion loss is 3.0–3.8 dB across 70–110 GHz, implying low loss and flat gain response.

Design Technique of K-Band CMOS Phase Shifter with L-C-L T-Type Low Pass Structure

In this study, we designed a 5-bit K-band CMOS switch type phase shifter. In order to minimize phase and gain errors, a design technique for bits constituting the phase shifter was proposed. The proposed design technique has been achieved by adjusting the resonant frequencies of inductance and capacitance in the L-C-L T-type low pass filter structure. Through this, a method of optimizing the phase shifter with the T-type low pass filter structure was presented. The K-band 5-bit phase shifter was designed with a 65 nm CMOS process to verify the feasibility of the proposed design technique. The core size was 0.78 × 0.21 mm2. At the frequency ranges of 22.0 to 23.0 GHz, the insertion loss and RMS phase and gain errors were measured to be 7.44 ± 2.0 dB, 2.6°, and 1.2 dB, respectively.

An offset and gain error calibration method in high-precision SAR ADCs

Successive approximation (SAR) ADC suffers from kinds of nonidealities such as offset and gain error which affect its absolute quantization range and reduce its performance in the high-precision applications. This paper presents a static offset and an embedded gain error calibration in analog domain, attempting to improve the conversion range error in SAR ADC architecture. The presented calibration technique reuses the CADC array, facilitating an analog-domain calibration within small dissipation.

A 28-GHz eight-element phased-array receiver front-end with compact size in 65-nm CMOS technology for 5G new radio

This article presents an 8-element 24–30-GHz phased-array receiver front-end in 65-nm CMOS technology for the millimeter-wave fifth-generation mobile network (5G). The phased-array receiver front-end is based on the radio-frequency (RF) phase-shifting architecture using RF vector-sum phase shifters with 5-bit phase resolution. The designed front-end can be easily expanded for use in large-scale phased arrays due to its compact size, low manufacturing costs, reasonable power consumption and low complexity. The post-layout simulations show a maximum single-element average gain of 12.85–15.7 dB across 5-bit phase states, with an associated noise figure (NF) of 6.15–7.5 dB and an input third-order intercept point (IIP3) value between –16.5 and –15.4 dBm. The simulated RMS gain and phase errors are less than 0.31 dB and 3°, respectively over 32 phase states and are constant over a 6-bit gain control. The designed eight-element phased-array receiver front-end has a total power consumption of 256±2.5 mW from a 1.2-V supply and occupies a small active area of 0.62 mm2.

The Impact of Beam Variations on Power Spectrum Estimation for 21 cm Cosmology. II. Mitigation of Foreground Systematics for HERA

One key challenge in detecting a 21 cm cosmological signal at z > 6 is to separate the cosmological signal from foreground emission. This can be studied in a power spectrum space where the foreground is confined to low delay (or, equivalently, k ∥) modes, whereas the cosmological signal can spread out to high delay modes. When there is a calibration error, however, the chromaticity of the gain errors propagates to the power spectrum estimate and contaminates the modes for cosmological detection. The Hydrogen Epoch of Reionization Array (HERA) employs a high-precision calibration scheme using redundancy in measurements. In this study, we focus on the gain errors induced by nonredundancies arising from a feed offset relative to HERA’s 14 m parabolic dish element and investigate how to mitigate the chromatic gain errors using three different methods: restricting baseline lengths for calibration, smoothing the antenna gains, and applying a temporal filter prior to calibration. With 2 cm/2° perturbations for translation/tilting motions, a level achievable under normal HERA operating conditions, the combination of the baseline cut and temporal filtering indicates that the spurious gain feature due to nonredundancies is significantly reduced, and the power spectrum recovers the clean foreground-free region. We found that the mitigation technique works even for large feed motions, but in order to keep a stable calibration process, the feed positions need to be constrained to 2 cm for translation motions and 2° for tilting offset relative to the dish’s vertex.

Nested-Oversampling Successive Approximation (OSA) Technique for Readout Circuit of MEMS Capacitive Accelerometer

Nested oversampling successive approximation (Nested-OSA) technique is proposed in this paper. This technique provides enhancement in the effective accuracy of the readout circuit for microelectromechanical systems (MEMS) capacitive accelerometer. The readout circuit with Nested-OSA technique contains a main switchedcapacitor amplifier which achieves capacitance-to-voltage conversion and an auxiliary switched-capacitor amplifier which suppresses the “holding error” appears in OSA process. The approach reduces the DC gain error and DC offset of amplifier to 4-order infinitesimal and 2-order infinitesimal. The charge injection and dynamic settling process of the Nested-OSA readout circuit are explained in detail. Theoretical analysis and simulations show that the suppression of gain error and offset of readout circuit using the Nested-OSA technique can be achieved while consume relatively low power.

Low-Rank and Row-Sparse Decomposition for Joint DOA Estimation and Distorted Sensor Detection

Distorted sensors could occur randomly and may lead to the breakdown of a sensor array system. We consider an array model within which a small number of sensors are distorted by unknown sensor gain and phase errors. With such an array model, the problem of joint direction-of-arrival (DOA) estimation and distorted sensor detection is formulated under the framework of low-rank and row-sparse decomposition. We derive an iteratively reweighted least squares (IRLS) algorithm to solve the resulting problem. The convergence property of the IRLS algorithm is analyzed by means of the monotonicity and boundedness of the objective function. Extensive simulations are conducted regarding parameter selection, convergence speed, computational complexity, and performances of DOA estimation as well as distorted sensor detection. Even though the IRLS algorithm is slightly worse than the alternating direction method of multipliers in detecting the distorted sensors, the results show that our approach outperforms several state-of-the-art techniques in terms of convergence speed, computational cost, and DOA estimation performance.

A 148–170‐GHz 4‐bit variable gain amplifier with stagger‐tuning and multistage‐phase‐compensation techniques in 0.13‐μm SiGe

AbstractThis letter presents a 148–170‐GHz 4‐bit variable gain amplifier (VGA) with stagger‐tuning and multistage‐phase‐compensation techniques. In the design of this proposed VGA, phase variation is minimized by cascading overcompensation VGA and undercompensation VGA with reverse gain‐phase characteristics and phase suppression characteristics at sideband, achieved through different shunt inductors to ground. Additionally, stagger‐tuning technique has been introduced to realize VGA design. To prove these techniques, a 148–170‐GHz 4‐bit VGA has been fabricated in 0.13‐μm SiGe bipolar complementary metal‐oxide‐semiconductor (350/450 GHz ft/fmax) with a compact size of . The results show the VGA achieves phase variation and over 10‐dB tuning range with 0.6‐dB gain step for a wide operating frequency from 148 to 170 GHz. The RMS gain error is dB, the simulated input is dBm and the total power consumption is 32.4‐mW with 2.25 V supply voltage.

A low-power mm-wave reduced-noise active balun with low-phase and low-gain error using common-gate shorting and DeQ inductor technique

This paper presents a low-power low-phase (gain) error (PE/GE) mm-wave active balun, using a common-source common-source (CS-CS) pair and cascode transistors with common-gate-shorting and deQ inductor (CGS-deQ) technique for error compensation. An inductor-capacitance-inductor T-network reduces (increases) the noise figure (gain) by about 3-dB (1.5-dB). Using a 180-nm CMOS technology with 1.8-V supply voltage, the balun achieves an area of 0.348 mm2, including the pads. The electromagnetic (EM) post-layout simulations show a maximum single-ended voltage gain of 18.23-dB, an IIP3 (IIP2) of −3.53-dBm (88.66-dBm) at the center frequency of 35-GHz, a PE (GE) under 1° (0.16-dB), and a noise figure between 5.9–6.9-dB over a 3-dB bandwidth from 33 to 37-GHz, with 6.9-mW power consumption. The proposed balun is compared to conventional common-gate common-source and CS-CS structure with/without CGS-deQ inductor technique for phase/gain error correction. Additionally, it is shown that this technique is insensitive to process-voltage-temperature (PVT) variations. The balun can also provide accurate differential signals for low RF frequencies.

An Active Reconfigurable Intelligent Surface Utilizing Phase-Reconfigurable Reflection Amplifiers

Active reconfigurable intelligent surfaces (RISs) have recently been proposed to complement and generalize passive RIS. In this work, the design for an active RIS based on phase-reconfigurable reflection amplifiers is proposed. The proposed active RIS elements’ design consists of a two-layer patch antenna and a phase-reconfigurable reflection amplifier that is realized by a cascade of a phase shifter and a reflection amplifier. Theoretical and numerical analyses are used to quantify key parameters that need to be met in the design of the reflection amplifier and phase shifters. These show that a tradeoff between the reflection amplifier’s gain and the phase shifter’s return and insertion loss is required to be balanced to obtain a stable and effective overall design. In particular, a reflection amplifier with about 13-dB gain and a 2-bit phase shifter with only about 1.9-dB insertion loss and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 25-dB return loss are designed. The final RIS element obtains 8.5-dB gain with four reconfigurable phases ranging from 0 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> to 360 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> with small root mean square (rms) gain and phase errors. An active RIS can be constructed by concatenating these elements together, and an efficient analytical method to calculate the scattered pattern by the active RIS is also proposed. Experimental results for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2$</tex-math> </inline-formula> element active RIS prototype are also provided. These show that the active RIS provides received powers around 8.5 dB higher than that from using an equivalent passive RIS. The results demonstrate the feasibility of achieving gain in active RISs and help demonstrate their promise as a technology for future high-capacity wireless communication systems.

60 GHz 7-Bit Passive Vector-Sum Phase Shifter With an X-Type Attenuator

This letter presents the design of a 60 GHz passive vector-sum phase shifter with 7-bit phase resolution. An analog X-type attenuator with complementary voltage control was used for vector modulation. The proposed attenuator is suitable for high-resolution phase shifter design because it is capable of phase inversion and shows a large attenuation range with low-phase variation. The prototype phase shifter fabricated through the 65 nm CMOS process occupies an area of 0.24 mm2 (excluding the bonding pads). The measurement results show that the proposed phase shifter achieves a phase resolution of 2.815∘ while exhibiting an average insertion loss of 14 dB without DC power consumption. The calculated RMS gain and phase error were below 0.55 dB and 0.83-2.36∘, respectively, in the range of 57-67 GHz.

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.

An Advanced Non-Interrupted Internal Calibration Model Based on Azimuth Modulation and Waveform Diversity for SAR Systems

Internal calibration, designed for obtaining the gain and phase errors introduced by the fluctuations of the electronic instruments, is an essential operation to guarantee the imaging performance of modern synthetic aperture radar (SAR) systems. However, in most of the current internal calibration schemes, the internal calibration processes interrupt the normal SAR data acquisition, which results in a loss of azimuth samples and degradation of the SAR image quality. To this end, an advanced non-interrupted internal calibration model is proposed, performing the internal calibration during nominal data acquisitions. The calibration signals and echoes are orthogonal and are received simultaneously. Then, they can be separated by postprocessing via the waveform diversity concept. Two schemes based on the proposed model are demonstrated via theoretical analysis and simulation experiments. The proposed model can achieve a considerable signal-to-noise ratio (SNR) and reduce the influence of calibration signals on echoes, which have some potential applications for future SAR missions.

Bias of the independently based gain and offset error in ADC testing using the histogram method

When normally distributed additive noise is present on the test setup, it leads to a bias on the values of estimated gain and offset error of analog-to-digital converters when estimated using the Histogram Test Method. It is shown that the offset estimation is unbiased while the gain estimation can have up to 5% bias for values of signal-to-noise ratio as low as 10 dB. It is also shown that this bias is not dependent on the number of samples acquired. An approximate analytical expression, in closed form, is proposed for rapid estimation of gain error. It considers the signal-to-noise ratio as well as the amount of overdrive used. The analytical derivations made are validated using simulated data using a Monte Carlo procedure. The same procedure is used with experimental data obtained with a real data acquisition system to validate the results obtained.

Fiber Raman Amplifier Based on Improved Whale Algorithm

In this paper, an improved whale algorithm to optimize pump power and wavelengths of second-order fiber Raman amplifier (FRA) has been proposed. Adopted by the strategies of adaptive gradients and reverse learning, the normal whale algorithm is greatly improved. An optimized FRA is designed based on the six-wavelength backward pump structure. Compared by optimizing both wavelength and power with optimizing only power, the gain flatness curves of the two algorithms, the optimal combination scheme, and the corresponding noise characteristics are got. A 6-pumped FRA has been designed in which the error of on-off gain is 0.08% and the ripple is only 0.18dB.

Gain Fault Detection Method for 3-phase AC Current Sensors

This paper proposes a novel method for detecting the gain fault of 3-phase AC current sensors in power electronics systems. In conventional methods, the sensor gain fault is detected by comparing the RMS values of the detection current of each phase. However, for an unbalanced three-phase load, a higher current will flow in the phase with the lower impedance, which causes misdiagnoses. In contrast, the proposed method utilizes the product of the detection current in each phase and sum of the detection current as part of the abnormality calculation (gain error calculation) of each current sensor, which can reduce calculation errors caused by an imbalance in the three-phase load. Simulation results show that the method can calculate the abnormality of the sensors with small error even if there is an imbalance in the three-phase load. Moreover, simulation results under conditions of varying current amplitude and frequency indicates that the method can detect sensor faults under transient conditions.

Design of a LDO with High PSRR

One of the common ways to increase the PSRR(power supply rejection ratio) of LDO (low dropout linear regulator) is increasing the gain of error amplifier, but the stability of LDO system will also be reduced. A new high gain error amplifier is designed to push the poles inside the amplifier away from the origin, which ensures the stability of LDO system and improves the PSRR of low frequency band. At the TT process corner, the range of adjustable output voltage of LDO is 1.361~1.860 V under the simulation condition of 27 °C. When power supply ranges from 2.3 V to 3.3 V, the linear regulation rate is 238.3 µV/V; When the load changes from 0 to 20 mA, the load regulation rate is 9.6 µV/mA; At load current of 20 µA, the power supply rejection ratio of LDO is -97 dB@dc, and the phase margin of the whole circuit is greater than 66 degrees. The chip is verified in a 0.18 µm CMOS process. Setting the power supply voltage in the range of 2.3 to 3.3 V, the output voltage is stable at 1.8 V, and the error is only 1.9 mV, which is less than 0.2%.

A 17.8-20.2 GHz Compact Vector-Sum Phase Shifter in 130 nm SiGe BiCMOS Technology for LEO Gateways Receivers.

This paper presents a novel and compact vector modulator (VM) architecture implemented in 130 nm SiGe BiCMOS technology. The design is suitable for use in receive phased arrays for the gateways of major low Earth orbit (LEO) constellations that operate in the 17.8 to 20.2 GHz frequency range. The proposed architecture uses four variable gain amplifiers (VGA) that are active at any given time and are switched to generate the four quadrants. Compared to conventional architectures, this structure is more compact and produces double the output amplitude. The design offers 6-bit phase control for 360°, and the total root mean square (RMS) phase and gain errors are 2.36° and 1.46 dB, respectively. The design occupies an area of 1309.4 μm × 1783.8 μm (including pads).

Three-Stage Operational Amplifier with Frequency Compensation Using Cascade Zero

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.