GaAs pHEMT Research Articles

A 2.4–4-GHz Wideband 7-Bit Phase Shifter With Low RMS Phase/Amplitude Error in 0.5-μm GaAs Technology

This article presents a 2.4–4-GHz wideband 7-bit switch-type phase shifter (STPS) with a switch driver. Three switch-type phase shifting topologies are employed for the design of the phase shifter (PS), including the switched <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L/C$ </tex-math></inline-formula> structure, T-type structure, and high-/low-pass network. For minimizing the phase and amplitude deviations, an improved T-type structure with a switched filter structure has been proposed to boost the performance of the PS. Besides, a phase compensation cell also has been adapted to further decrease the phase error of the STPS. Based on the topology choice of each cell and the amplitude compensation among cells, a systematic design method is developed to extend the bandwidth of the PS. The proposed 7-bit STPS was implemented in the 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The measured root-mean-square (rms) phase error of the proposed STPS is less than 3.1° from 2.4 to 4 GHz and less than 1.5° at 2.8–3.7 GHz. The average insertion loss (IL) is 4.5–4.9 dB with an rms amplitude error of less than 0.34 dB. IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is about 30 dBm. To the best of our knowledge, this PS achieves the highest resolution and the lowest rms amplitude error among the published GaAs/GaN PSs over a similar frequency band. The IL, bandwidth, and rms phase error of the proposed PS also show good performance.

A 37-GHz Asymmetric Doherty Power Amplifier With 28-dBm P sat and 32% Back-Off PAE in 0.1-μm GaAs Process

In this article, the analysis, design, and development of a 37-GHz asymmetric Doherty power amplifier (DPA) are presented. In a practical DPA, the main power amplifier (PA) shows nonideal characteristic, which varies the effect of the load modulation. Based on the theoretical analysis, we derive the relationship among the efficiency, power back-off (PBO) level, and the corresponding load impedance in a nonideal load modulation. The result suggests that a Class-AB main PA shows a decreased PBO efficiency during the load modulation. To achieve a good compromise between PBO level and PBO efficiency of the main PA, the load modulation scheme is redesigned in this work. A 2-dB PBO of the main PA is chosen to maintain the high efficiency during the load modulation. An asymmetric DPA topology is employed to compensate the inadequate PBO of the main PA so that a desired 6-dB PBO is achieved. Generally, the RF leakage at the DPA output degrades its performance. To solve this issue, we propose a modified low characteristic impedance DPA output network. The output matching network of the auxiliary PA is particularly designed to enlarge its output impedance. Through these design techniques, the leakage loss is significantly reduced to 0.2 dB, which improves the gain and power-added efficiency (PAE) at PBO. To validate the proposed techniques, a DPA chip is designed and fabricated in a D-mode 0.1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pHEMT process. At 37 GHz, the 1.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm integrated chip exhibits a measured small-signal gain of 15.6 dB and a saturated power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$ </tex-math></inline-formula> ) of 28.0 dBm, with an associated 33.2% peak PAE and a 32.0% PAE at 6-dB PBO. To the best of our knowledge, the proposed chip exhibits the state-of-the-art overall performance among DPAs operating around 37 GHz for 5G n260 millimeter-wave (mm-wave) band.

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process.

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

Ultralow-Power Digital Control and Signal Conditioning in GaAs MMIC Core Chip for X-Band AESA Systems

This work presents the design and characterization of an ultralow-power core chip for electronically scanned arrays at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula> -band, implemented in 0.25-/0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> E-/D-mode gallium arsenide (GaAs) pHEMT technology. In particular, design details are given about the two core functional blocks embedded in the microwave monolithic integrated circuit (MMIC): a 12-bit phase and amplitude control circuit and an 18-bit serial-to-parallel (S2P) interface. The S2P interface was designed resorting to a custom symmetric device model, expressly conceived for the time-domain simulations required for digital circuits. Due to the adoption of a differential structure with resistive pull-ups, it achieves a state-of-the-art power consumption of 2.2 mW/bit and nearly 87% yield. The analog circuit includes a 6-bit phase shifter (PS) and a 6-bit attenuator. To mitigate risks, two different PS architectures have been developed and are compared in this work, discussing advantages and drawbacks of the different solutions. Since the two designs share the same target specifications, a truly fair comparison can be made not only in terms of performance but also concerning robustness and repeatability, thus providing useful guidelines for the selection of the most appropriate strategy. In particular, it is shown that one architecture outperforms the other by about 2 dB and 1.5° in terms of insertion loss and rms phase error, respectively.

Design of a Compact Dual-Band Absorptive Single-Pole Double-Throw Switch

In this letter, a compact dual-band absorptive single-pole double-throw (SPDT) switch design is proposed. It utilizes the bridged-T coil as a miniaturized dual-band <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda /4$ </tex-math></inline-formula> transformer such that the concurrent dual-band operation in the on-state and the desired absorptive property in the off-state can be both achieved. The proposed design concept is validated through a 2.45/5.8-GHz dual-band absorptive SPDT switch design implemented in a commercial GaAs pHEMT process. The measured on-state insertion loss is 1.54/1.97 dB and the off-state isolation is 35/29 dB at 2.45/5.8 GHz, while the measured return losses at all ports are better than 20 dB at 2.45/5.8 GHz. In addition, a compact chip size of 2.0 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.5 mm is achieved.

Highly Selective Bandpass Switch Block With Applications of MMIC SPDT Switch and Switched Filter Bank

A new bandpass single-pole single-throw (SPST) switch (BPSW) is proposed in this letter. The proposed BPSW configuration can be directly employed as a building block to construct the single-pole N-throw (SPNT) switch or the highly-selective switched filter bank with no need for the extra control circuit, thus effectively reducing the circuit size and lowering the loss. The operation mechanism of the BPSW is analyzed, and the filter-synthesis-based design method is given. For demonstration, 3-6 GHz and 4-8 GHz BPSW blocks are built using the commercial GaAs pHEMT process to construct the single-pole double-throw (SPDT) switch as well as the two-way integrated switched filter bank. The filter bank is implemented in 0.25 &#x03BC;m GaAs pHEMT process. Two passbands are measured at 2.7-5.79 GHz and 3.72-7.35 GHz with a minimum insertion loss of 2.7 dB, while the all-OFF state can be set with over 35 dB suppression. The measurement results are in good agreement with the simulation that verifies the concept.

A V-Band Integrated Receiver Front-End Based on 0.15 μm GaAs pHEMT Process for Passive Millimeter-Wave Imaging

The design, analysis, implementation and measurement of an integrated V-band receiver front-end based on 0.15 &#x03BC;m GaAs pHEMT process are presented in this paper. The front-end chip uses the super-heterodyne topology which consists of a low noise amplifier, an image reject mixer, and a multiply-by-four (&#x00D7;4) LO chain. In order to minimize the power consumed by LO chain, an active single-ended mixer is designed which requires extremely low LO power of -5 dBm. Meanwhile, the effect of signal coupling in the integrated chip is analyzed and solutions are proposed. By introducing appropriate filters into the circuit and optimizing the overall layout, the imbalance of in-phase and quadrature signals caused by unwanted coupling can be effectively mitigated, thus enhancing the image rejection of the chip. Probe and module tests are applied to the receiver front-end, and the measurement results reveal that the chip achieves -3 &#x00B1; 0.7 dB conversion gain, 7 dB noise figure and more than 25 dB image rejection ratio in the RF frequency range of 52-56 GHz. Only one supply voltage of 3 V is required for the chip, and total power consumption is 312 mW. Moreover, with a continuously adjustable phase control of 360&#x00B0; and very broadband IF characteristics, the front-end chip is suitable for passive millimeter-wave imaging applications.

Development of a 0.15 μm GaAs pHEMT Process Design Kit for Low-Noise Applications

This work presents a process design kit (PDK) for a 0.15 μm GaAs pHEMT process for low-noise MMIC applications developed for AWR Microwave Office (MWO). A complete set of basic elements is proposed, such as TaN thin film resistors and mesa-resistors, capacitors, inductors, and transistors. The developed PDK can be used in technology transfer or education.

A Broadband Gain Amplifier Designed with the Models for Package and Diode Using 0.5 μm GaAs E-pHEMT Process

This paper presents a 50 MHz to 5 GHz broadband gain amplifier using a 0.5 μm gallium-arsenide pseudomorphic high-electron-mobility-transistor (GaAs pHEMT). For broadband design, a high gain cascode structure with a feedback network was used. To ensure the robustness of the design, the amplifier had to consider the effects of the Electrostatic Discharge (ESD)-protected diode and the package, which can degrade the broadband performance. Therefore, the equivalent circuit models of the package and the ESD-protected diode were analyzed and simulated in this paper. The designed broadband gain amplifier from 50 MHz to 5 GHz frequency band has a die size of 700 μm × 1000 μm and consumes 156 mW of dc power, and it was simulated with a gain of 18.7 dB to 20.6 dB, a P1dB of 15.3 to 16.9 dBm, and a OIP3 of 26.5 to 31 dBm. Furthermore, the excellent gain flatness exhibited within 18.7 dB ± 1.92 dB at the interest of the frequency band.

A compact model for dual-gate GaAs PHEMT and application for power amplifier design

A compact model for dual-gate GaAs PHEMT and application for power amplifier design

Integrated balanced homodyne photonic–electronic detector for beyond 20 GHz shot-noise-limited measurements

Optical homodyne detection is used in numerous quantum and classical applications that demand high levels of sensitivity. However, performance is typically limited due to the use of bulk optics and discrete receiver electronics. To address these performance issues, in this work we present a co-integrated balanced homodyne detector consisting of a silicon photonics optical front end and a custom integrated transimpedance amplifier designed in a 100 nm GaAs pHEMT technology. The high level of co-design and integration provides enhanced levels of stability, bandwidth, and noise performance. The presented detector shows a linear operation up to 28 dB quantum shot noise clearance and a high degree of common-mode rejection, at the same time achieving a shot-noise-limited bandwidth of more than 20 GHz. The high performance of the developed devices provide enhanced operation to many sensitive quantum applications such as continuous variable quantum key distribution, quantum random number generation, or high-speed quantum tomography.

A Low Insertion Loss Variation Trombone True Time Delay in GaAs pHEMT Monolithic Microwave Integrated Circuit

A wideband true time delay is proposed based on 0.25- μm GaAs pHEMT technology. The novel trombone topology is adopted for achieving low variation in insertion loss of different delay states. The fourth-order and second-order inductive all-pass networks (APNs) are operating as delay cells between input and output lines. By selecting different transmission ways, 3 bit with the step of 14 ps and maximum delay range of 98 ps are realized. Measurement results show the insertion loss of 3.8-10.5 dB over the frequency bandwidth of 6-16 GHz. The variation in insertion loss is less than ±1.4 dB. The chip area with pads is 1.955 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is 110 mW.

Automated design of a linear microwave monolithic distributed amplifier

Microwave integrated circuit (IC) design tends to become more efficient and less expensive which leads to emerging the circuit topology and layout synthesis software. In the paper we present a technique and an algorithm for microwave distributed amplifier (DA) automated synthesis based on requirements to linear characteristics. The technique feature is the using of active and passive element’s models for a chosen IC process. This allow the technique to generate circuit topology which can be manufactured using a given IC process. The proposed DA automated design technique work was demonstrated with preamplifier stage design for 20–30 GHz buffer amplifier MMIC based on the 0.25um GaAs pHEMT process of Svetlana-Rost foundry in Saint-Petersburg.

Low Noise and high linearity Wide band Low Noise Amplifier for 5G Receiver Front End System

This work Demonstrates a wideband LNA for 5G receiver front end modules with high linearity, Low noise reused topology has an inter stage wideband inductor based two common source cascade stages. The configuration provides the bias current; better Noise figure increases the forward gain. By providing RC Series network at gate terminal of second stage the return losses are reduced and stability will be increased. After pre and post simulation all parameters are better than the existing LNAS. After post simulation results, the Noise figure is achieved less than 1dB and forward gain as flat 16dB for wide band width of 1.5 – 5.5 GHz. At the 1dB compression point the output is 20dbm achieved and OIP3 IS +40dbm is achieved. The chip size of an LNA along with pad is 0.64mm2. The design is GaAsp HEMT process at 50nm technology.

A W‐band preamplified MMIC power detector for passive imaging applications

AbstractThis article presents a W‐band preamplified power detector (PD) monolithic microwave integrated circuit (MMIC). The chip consists of a pseudomorphic high electron mobility transistor (pHEMT) PD with a six‐stage low noise amplifier (LNA) in a commercial 0.1‐μm GaAs pHEMT technology. In order to reduce the high risk of oscillating in a multistage LNA, a circulator‐based method for LNA interstage stability simulation, along with the concept of loop gain, is introduced and analyzed. The simulated loop gain of each node of the LNA is calculated through the proposed method to ensure the unconditional stability for the six‐stage LNA. By incorporating the high gain LNA over 32 dB in the front‐end of the PD, the measured chip achieves a peak responsivity of 3.4 MV/W and a minimum noise equivalent power (NEP) of 95 fW/Hz1/2 both at 85 GHz. To the best of the authors' knowledge, the proposed PD exhibits the best responsivity and NEP in published W‐band GaAs PD MMICs.

Stabilisation of multi‐loop amplifiers using circuit‐based two‐port models stability analysis

This article applies a systematic approach based on the normalized determinant function (NDF) theory to analyse stability in multi-loop circuits and to design the required stabilization network. Presenting several provisions, the return ratios are extracted by employing immittance or hybrid matrices (Z, Y, G or H) of active two ports. Using these matrices, instead of the S-parameters, facilitates the selection of an appropriate stabilizer network. As a practical case, a non-uniform distributed amplifier (NDA) is designed and inspected for potential instabilities. The presented procedure detects instability associated with one of the NDA circuit's loops, and an appropriate stabilization circuit is accordingly devised. In order to validate the procedure, the designed NDA is implemented in a 0.1-μm GaAs pHEMT process. As predicted, the measurements show oscillations, once the on-chip stabilization circuit is disabled.

A Ka-Band Switchable LNA With 2.4-dB NF Employing a Varactor-Based Tunable Network

This letter presents a multiband switchable low-noise amplifier (LNA) in the 0.1- μm GaAs pHEMT process. Employing a new varactor-based tunable network as the interstage matching circuit, the operation bands can be tuned consecutively and cover the 5G millimeter-wave frequency bands N257/N260. The proposed tunable structure functions well without sacrificing noise performance or increasing dc consumption and chip area. In the entire operation band from 26.5 to 41 GHz, the LNA achieves a small-signal gain of over 24 dB and a noise figure (NF) of less than 2.9 dB. The measured result shows a small-signal gain of 25.1 dB/27.7 dB and an NF of 2.4 dB/2.8 dB at 28 GHz/39 GHz. The measured input 1-dB compression point (IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ) is -18.3 dBm/-17 dBm at 28 GHz/39 GHz. The measured input-referred intercept point (IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) is -8.8 dBm/-8.5 dBm at 28 GHz/39 GHz. The LNA has a chip size of 1.6 mm ×1 mm, and the total power consumption is 74 mW. To the best of our knowledge, the proposed LNA is the state-of-the-art Ka-band switchable LNA and has similar performance compared with single-band LNAs using the same technology.

A Miniaturized Bandwidth Reconfigurable Bandpass Chip Filter with Semi‐lumped Topology and GaAs pHEMT Technology

A miniaturized reconfigurable bandpass chip filter with semi-lumped topology and Gallium Arsenide pseudomorphic High electron mobility transistor (GaAs pHEMT) technology is proposed. Semi-lumped topology is employed to instead the traditional lumped inductor with microstrip transmission line, which can reduced the size of the tunable filter significantly. Three-order series and shunt resonated bandpass filter is implemented with shorted stubs and metal-insulator-metal capacitors. Two transmission zeros are introduced with the series resonator and the shunted GaAs FET. By tuning the gate bias circuit of the FET, the capacitance of the series resonator is changed and the bandwidth of the filter is adjusted correspondingly. An equivalent circuit model is developed to interpret the mechanism of the proposed filter circuit. A reconfigurable on chip filter sample operated at 10GHz is fabricated to validate the design. Two fractional bandwidth of 14.3% and 23.5% are tuned with bias voltage of the FET, while insertion loss of 2.4dB and 2.2dB are observed with the filter, respectively. The area of the chip filter is \begin{document}$ {{0.86 \times 0.96 \mathrm{mm}^{2}}} $\end{document} and is equivalent to an electrical length of \begin{document}$ {{0.08 \times 0.09 \lambda \mathrm{g}^{2} }}$\end{document} at center frequency. Measurement results agree well with the simulation ones.

A GaAs p-HEMT Distributed Drain Mixer With Low LO Drive Power, High Isolation, and Zero Power Consumption

This paper presents a balanced distributed drain mixer fabricated in a 0.25-μm GaAs p-HEMT technology. The balanced distributed mixer combines two single-ended distributed mixers with an on-chip RF balun and LO divider integrated for improving isolation performance. Each single-ended mixer is designed with three drain-mixing unit cells distributed along transmission lines for broadband operation. The transistor size, bias condition and transmission line lengths are analyzed and determined to improve the conversion gain, bandwidth and impedance matching. In addition, the LO drive power required for mixing operation is reduced by bias optimization and large-signal LO matching. The balanced distributed drain mixer exhibits measured conversion gain of -4.0 to -7.4 dB from 5.4 to 21.8 GHz. The LO drive power of the mixer is as low as 2 dBm. The LO-to-RF and LO-to-IF isolation are higher than 23.5 and 54.7 dB, respectively. The mixer consumes no dc power due to the passive drain-mixing topology.

Design of 35-dB 0.03-to-2.7 GHz Two-Stage Broadband Power Amplifier With 37.2 dBm Psat Using Modular Technology

This paper presents a modular technology for two-stage broadband power amplifier (PA) design. The proposed method focuses on separately realizing two stage’s flat gain characteristics, thus providing the entire circuit’s required flatness over broad bandwidth. The power stage employs stacked structure to provide enough power and confine the output impedance around $50~\Omega $ , while the driver stage’s periphery is selected to achieve impedance transformation demanded by modularization. The elaborate requirements for input and inter-stage matching networks (MNs) are repeatable which can be synthesized by real frequency technique (RFT), shortening the design time of broadband MNs. The modular approach can also be transferred to the implementation of other broadband PAs. This novel technology was verified using $0.25~\mu \text{m}$ GaAs PHEMT process. The fabricated two-stage broadband PA obtains a small-signal gain higher than 35.0 dB and saturated output power of 37.2± 1.6 dBm from 30 MHz to 2.7 GHz, with a peak power added efficiency (PAE) of 46.2% at 500 MHz. To our knowledge, this is the highest gain and output power in GaAs broadband amplifier below 2.7 GHz.