Abstract
This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.
Highlights
With the continuous development of integrated circuit technology, phase-locked loop (PLL) frequency source technology is widely used in various sensors, such as for highaccuracy clock generators for image sensors [1,2,3,4]
The proposed charge pump phase locked loop (CPPLL) is realized by cascading each module based on a 0.15 μm GaAs pHEMT process
Measurement results show that the operating frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, and the consumed power is 181 mW
Summary
With the continuous development of integrated circuit technology, phase-locked loop (PLL) frequency source technology is widely used in various sensors, such as for highaccuracy clock generators for image sensors [1,2,3,4]. Charge pump phase-locked loop (CPPLL) is a representative structure of PLL because of its low phase noise, variational phase difference, and high-frequency operation [6,7,8]. The operating frequency of the proposed PLL is about 37 GHz, the phase noise is −98 dBc/Hz at a frequency offset of 1 MHz, and the circuit consumes about 480 mW. It can be seen from the above references that GaAs pHEMT has the characteristics of high gain, excellent power characteristics, and low noise [15,16,17].
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