Fully-depleted SOI MOSFETs Research Articles

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

The trap-induced noise characteristics of fully-depleted SOI (FDSOI) MOSFETs with ultra-thin body and buried oxide are essential for high-performance applications. However, accurate noise modeling and traps identification of the device remains challenging. In this work, we investigate the noise characteristics of FDSOI MOSFETs arising from traps in both the gate dielectric (GD) and the buried oxide (BOX). By using TCAD tool, we examine the noise generated by traps at various energy levels and spatial positions in GD and BOX under different biases. The simulation results reveal that traps in GD and BOX exhibit distinctly different behaviors as Vg increases, providing insights for identifying traps from noise measurement results.

Analog and radio-frequency performance of nanoscale SOI MOSFET for RFIC based communication systems

Fully-Depleted (FD) Silicon-on-Insulator (FD SOI) MOS structures have attained remarkable attention due to its immunity over various short-dimension effects and lesser complexity in design as compared to other MOS structures like FinFET. In this work, Dual-Metal-Insulated-Gate (DMIG) technique based FD SOI MOSFETs have been analyzed for the study of low power Analog/RF applications. It has been found that the proposed hetero-gate-dielectric based DMIG source-engineered (HGD-DMIGSE) FD SOI MOSFET offers higher transconductance that allows higher gain and lowers the capacitive effects with broad-range of cutoff frequency as compared to available devices at same technology node. In next, the performance of the studied MOSFET has also been analyzed on the basis of admittance Y-parameters in order to investigate the device behaviour at higher frequencies. Further, for the first time, a current-source CMOS-inverter-amplifier has been designed using proposed HGD-DMIGSE FD SOI MOSFET. All these studies have been performed using ATLAS™ TCAD simulator.

Total Ionizing Dose Effects in FDSOI Compact Model for IC Design

The total ionizing dose (TID) is a well-known reliability issue for integrated circuits (ICs). It consists in changes of MOSFETs dc characteristics following the irradiation of devices in a given radiative environment, such as space environment. TID effects have been investigated from an experimental and theoretical standpoint, and the compact modeling of TID effects has been included into BULK transistor compact models using PSP formalism in the case of uniform and nonuniform energetic distributions of interface traps. However, TID effects are still not included in fully depleted SOI (FDSOI) standard models. In this paper, TID effects modeling is proposed and included in Leti-UTSOI compact model for FDSOI MOSFETs. This model takes both uniform and nonuniform energetic distributions of both gate oxide/silicon and silicon/buried oxide (BOX) interface traps into account, as well as the contribution of oxide/BOX-trapped charges. Validation of the model has been done through TCAD simulations, and we used this model to extract TID parameters from the experimental data.

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

The Drain Induced Barrier Lowering (DIBL) behavior in Ultra-Thin Body and Buried oxide (UTBB) transistors is investigated in details in the temperature range up to 150°C, for the first time to the best of our knowledge. The analysis is based on experimental data, physical device simulation, compact model (SPICE) simulation and previously published models. Contrary to MASTAR prediction, experiments reveal DIBL increase with temperature. Physical device simulations of different thin-film fully-depleted (FD) devices outline the generality of such behavior. SPICE simulations, with UTSOI DK2.4 model, only partially adhere to experimental trends. Several analytic models available in the literature are assessed for DIBL vs. temperature prediction. Although being the closest to experiments, Fasarakis’ model overestimates DIBL(T) dependence for shortest devices and underestimates it for upsized gate lengths frequently used in ultra-low-voltage (ULV) applications. This model is improved in our work, by introducing a temperature-dependent inversion charge at threshold. The improved model shows very good agreement with experimental data, with high gain in precision for the gate lengths under test.

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

Simulation Analysis of Narrow Width Effect in Nano Structured Fully Depleted SOI MOSFET

This paper is about the analysis of width effect in a narrow channel fully depleted SOI MOSFET. The effect of width variation is observed on threshold voltage of Nano structured Fully Depleted SOI MOSFET. In present analysis variation in narrow channel width and short channel length of the device reduced the threshold voltage . The channel conduction is also influence by changing the Tsi and Tox of the proposed device. The Lateral direction engineering is performed during the analysis of NSMOSFET(NanoStructured).

Accurate analytical drain current model for a nanoscale fully-depleted SOI MOSFET

This paper reports a closed-form analytical drain current model for a fully-depleted (FD) SOI MOSFET on the inversion region in nanoscale regime. The proposed analytical approach involves all the important physical models which are essential in the nanoscale structures. The analytical threshold voltage model is used to take into account the critical short channel effects (SCEs) for the nanoscale SOI MOSFETs. The proposed analytical drain current model considering lattice and electron temperatures, self-heating effect (SHE), nonlocal impact ionization and parasitic bipolar effect shows an excellent match with experimental data for a 40nm node technology. The realized analytical model is suitable for analyzing the devices with short and long channel lengths and therefore it can be considered as an efficient and flexible model to accurately predict the drain current of the FD-SOI devices.

Study of an embedded buried SiGe structure as a mobility booster for fully-depleted SOI MOSFETs at the 10 nm node

This paper presents mechanical simulations results of an innovative strain transfer structure consisting in a buried compressive SiGe layer embedded under an ultra-thin buried oxide (BOX). We studied the influence of different dimensions including the active area and determined optimal parameters of the SiGe layer maximizing the strain. We demonstrate a transfer of a tensile stress up to 1.3GPa in the silicon. Thanks to 3D simulations and the study of stress profiles in the SOI, the electron mobility enhancement is estimated to be about 80% for logic transistors at the 10nm node. The strain induced in the channel by the edge relaxation of an embedded buried SiGe layer is compared to strained Silicon-On-Insulator (sSOI) wafers and strained nitride layer for Fully Depleted Silicon-On-Insulator (FDSOI).

Optimization of SiC:P Raised Source Drain Epitaxy for Planar 20nm Fully Depleted SOI MOSFET Structures

This paper will focus on the capability of a low-temperature cyclical deposition/etch (CDE) epitaxy process based on Si2H6 to fabricate SiCP films exhibiting very-high, electrically-active P and C concentrations with fast growth rates. This process will be characterized on blanket wafers first and optimized for raised source/drain applications in planar FDSOI technology featuring 20nm design rules. Low temperature drive-in anneal in combination with high phosphorus doping was employed leading to best resistivity values of 0.3 mΩ.cm for SiP and 0.6 mΩ.cm for SiC2%P. We will show that increasing the phosphorus concentration in the layers enables us to have the same transistor overlap after diffusion anneal for comparable resistivity with SiP films and improved carbon substitutionality. Best Ron values as low as 220Ω.μm will be reported, measured on 20nm gate length transistors in planar FDSOI technology with an optimized process.

Optimization of SiC:P Raised Source Drain Epitaxy for Planar 20nm Fully Depleted SOI MOSFET Structures

not Available.

Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.

Compact Modeling for Submicron Fully Depleted SOI MOSFET's

In this paper, we have developed a novel compact charge-conservative model for fully depleted silicon-on- -insulator MOSFETs and implemented it in SPICE3. Our model is valid for the DC, small-signal and large-signal simulations over a wide range of temperature. Simulations made using the model, following parameter extraction, are validated by comparison with experimental data. near subthreshold slope, increased saturation current and re- duced parasitic capacitances. Moreover, SOI MOSFETs are suitable in high temperature applications since they present a low leakage current and a reduced soft error ef- fect (1). Hence the availability of accurate fully depleted (FD) SOI MOSFET device model is suitable to both dig- ital and analog circuit simulation for the emerging SOI technology. To address this need, we propose in this paper a com- pact model for FD SOI MOSFETs in strong inversion. In this model, a linear relationship between the surface potential and the inversion charge density is used. The drain current and the total charges are written in terms of the inversion charge densities at the drain and source ends of the channel. The explicit unified expression of the inversion charge density is applied in these equa- tions (2, 3). Therefore, this model can be used to cal- culate the drain current and all large and small signal parameters since it includes threshold voltage roll-o, parasitic source/drain resistance eect, mobility reduc- tion due to the vertical field, carrier velocity saturation

A Unified Analytical One-Dimensional Surface Potential Model for Partially Depleted (PD) and Fully Depleted (FD) SOI MOSFETs

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I– V and C– V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.

Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications

Even in fully-depleted (FD) SOI MOSFETs, the floating-body potential variations may lead to strong transient effects on the current characteristics. A physics-based model, enabling the fast computing of the potential variation with time, is proposed in this paper. The model is validated, for a wide range of technological parameters and biases, by 2D numerical simulations. This model reproduces the experimental data and clarifies the physics mechanisms responsible for the transient variations of gate and drain currents. Relevant applications in the field of EEPROM and capacitorless floating-body DRAM memories are addressed.

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

A simple analytical model for deriving the front and the back gate threshold voltages of a short-channel fully-depleted SOI MOSFET is presented. Taking into account the lateral variations of the front and the back surface potentials, we obtain two-dimensional potential distributions in the fully depleted silicon body, the front oxide layer, and the back oxide layer. From the obtained two- dimensional potential in the silicon body, the minimum values of both front and back surface potentials are derived and used to describe both front and back gate threshold voltages as closed-form expressions in terms of various device geometry parameters and applied bias voltages. Obtained results are found to be in good agreement with the numerically simulated results.

Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We show that more than 50% higher mobilities of electrons can be obtained as indicated by 3D simulations performed throughout the entire fabrication process. Then, fully-depleted SOI MOSFET and d-Dot MOSFET are compared in term of short channel effects, parasitic capacitance effects and self-heating effects.

High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs

For fully-depleted SOI MOSFETs, fabricated in standard and strained 65 nm technologies, it is observed that the drain current I normalized for the device length L and width W levels off at sufficiently high gate voltage overdrives. Also the normalized drain current 1/ f noise spectral density S I shows a plateau value for high front gate voltages. For both strained and non-strained devices there exists a relation between the two plateau values and a y ∼ ( x) 1/4 law is found for the experimental data where x = S I plateau ( L 3 / WN ot ) , y = I plateau ( L/t W), S I plateau and I plateau are the plateau values of S I and I, respectively, and N ot is the density of the oxide traps responsible for the 1/ f noise observed. Compared to standard SOI the use of strained SOI (sSOI) increases the magnitude of the plateau and makes its dependence on the device geometry more pronounced, while the impact of a strained contact etch stop layer (sCESL) is limited. The experimental observations are explained by taking into consideration the field and geometry dependence of the mobility and the influence of negative oxide charges on the drain current.