Compact Modeling for Submicron Fully Depleted SOI MOSFET's

Abstract

In this paper, we have developed a novel compact charge-conservative model for fully depleted silicon-on- -insulator MOSFETs and implemented it in SPICE3. Our model is valid for the DC, small-signal and large-signal simulations over a wide range of temperature. Simulations made using the model, following parameter extraction, are validated by comparison with experimental data. near subthreshold slope, increased saturation current and re- duced parasitic capacitances. Moreover, SOI MOSFETs are suitable in high temperature applications since they present a low leakage current and a reduced soft error ef- fect (1). Hence the availability of accurate fully depleted (FD) SOI MOSFET device model is suitable to both dig- ital and analog circuit simulation for the emerging SOI technology. To address this need, we propose in this paper a com- pact model for FD SOI MOSFETs in strong inversion. In this model, a linear relationship between the surface potential and the inversion charge density is used. The drain current and the total charges are written in terms of the inversion charge densities at the drain and source ends of the channel. The explicit unified expression of the inversion charge density is applied in these equa- tions (2, 3). Therefore, this model can be used to cal- culate the drain current and all large and small signal parameters since it includes threshold voltage roll-o, parasitic source/drain resistance eect, mobility reduc- tion due to the vertical field, carrier velocity saturation