Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

Abstract

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.