32 nm Gate Length FinFET: Impact of Doping

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ABSTRACT FinFET, a self–aligned double-gate MOSFET structure has been agreed upon to eliminate the short channel effects. In this thesis, we report the design, fabrication and physical characteristics of n-channel FinFET with physical gate length of 32nm using visual TCAD (steady state analysis). All the measurements were performed at a supply voltage of 1.5V and T ox =5nm. We elucidate the impact of doping concentration on the Performance of n-channel 32nm gate length FinFET at 22nm width. The drain current increases gradually when donor ion concentration in source/drain regions increases to 7e20 cm -3 . Adding opposite type of source/drain impurity or decreasing acceptor ion concentration in channel further improves the performance of FinFET. Keywords FinFETs; CMOS; Drain Induced barrier lowering; Silicon-on-insulator 1. INTRODUCTION SOI (silicon on Insulator) basis multi-gate transistor structure is advisable for miniaturization of transistors and adequate for conquering short channel effects [1]. Fragile structured SOI devices are encouraging for escalating CMOS devices into nano-scale regime. One of them is dual-gate FinFET, includes a steep Si fin restrained by self-aligned double gate [2]. The FinFET technology is enticing because the procedure is accessible to implement with existing processing approaches [3]. The technology consists of developing a slender silicon island (fin) by engraving the silicon film [3]. Some of the essential aspects of FinFET are ultra thin Si fin for elimination of short channel effects, lifted source/drain to cut down parasitic resistance and revamp drive current [2]. FinFETs exploit symmetric gates to achieve tremendous performance, but can be fabricated with asymmetric gates so as to target threshold voltage [4]. FinFETs are drafted to benefit numerous fins to attain larger channel widths [4, 5]. Source/Drain pads bridge the fins in parallel. Increment in number of fins leads to boost the current through the device [4, 5]. For example, a device having five fins has five times higher current than single fin device [4]. The leading asset of the FinFET is the ability to exceptionally lower the short channel effects [2, 3, and 4]. In spite of double gate structure, the FinFET is related to its essence, the conventional MOSFET in layout and fabrication [2]. Three dimensional FINFET design is shown in Fig. 1. FINFET comprises a narrow perpendicular fin placed on the exterior of the wafer. Source and drain are crosswise on both sides of fin. This structure is positioned on SOI substrate.