Front-end ASIC Research Articles

Design of a Multi-Channel Low-Noise Readout ASIC for CdZnTe-Based X-Ray and <formula formulatype="inline"><tex Notation="TeX">$\gamma $</tex></formula>-Ray Spectrum Analyzer

In this paper, we report on the recent development of a 32-channel low-noise front-end readout ASIC for cadmium zinc telluride (CdZnTe) X-ray and $\gamma $ -ray detectors. Each readout channel includes a charge sensitive amplifier, a CR-RC shaping amplifier and an analog output buffer. The readout ASIC is implemented using TSMC $0.35 - \mu \hbox{m}$ mixed-signal CMOS technology, the die size of the prototype chip is $2.2~\hbox{mm} \times 4.8~\hbox{mm}$ . At room temperature, the equivalent noise level of a typical channel reaches $133~\hbox{e}^ - ({\rm rms})$ with the input parasitic capacitance of 0 pF for the average power consumption of 2.8 mW per channel. The linearity error is less than $ \pm 2\% $ and the input energy dynamic range of the readout ASIC is from 10 keV to 1 MeV. The crosstalk between the channels is less than 0.4%. By connecting the readout ASIC to a CdZnTe detector, we obtained a $\gamma $ -ray spectrum, the energy resolution is 1.8% at the 662-keV line of $^{137}{\rm Cs}$ source.

Use of high-granularity CdZnTe pixelated detectors to correct response non-uniformities caused by defects in crystals

Following our successful demonstration of the position-sensitive virtual Frisch-grid detectors, we investigated the feasibility of using high-granularity position sensing to correct response non-uniformities caused by the crystal defects in CdZnTe (CZT) pixelated detectors. The development of high-granularity detectors able to correct response non-uniformities on a scale comparable to the size of electron clouds opens the opportunity of using unselected off-the-shelf CZT material, whilst still assuring high spectral resolution for the majority of the detectors fabricated from an ingot. Here, we present the results from testing 3D position-sensitive 15×15×10mm3 pixelated detectors, fabricated with conventional pixel patterns with progressively smaller pixel sizes: 1.4, 0.8, and 0.5mm. We employed the readout system based on the H3D front-end multi-channel ASIC developed by BNL's Instrumentation Division in collaboration with the University of Michigan. We use the sharing of electron clouds among several adjacent pixels to measure locations of interaction points with sub-pixel resolution. By using the detectors with small-pixel sizes and a high probability of the charge-sharing events, we were able to improve their spectral resolutions in comparison to the baseline levels, measured for the 1.4-mm pixel size detectors with small fractions of charge-sharing events. These results demonstrate that further enhancement of the performance of CZT pixelated detectors and reduction of costs are possible by using high spatial-resolution position information of interaction points to correct the small-scale response non-uniformities caused by crystal defects present in most devices.

Performance of fully instrumented detector planes of the forward calorimeter of a Linear Collider detector

Detector-plane prototypes of the very forward calorimetry of a future detector at an e+e− collider have been built and their performance was measured in an electron beam. The detector plane comprises silicon or GaAs pad sensors, dedicated front-end and ADC ASICs, and an FPGA for data concentration. Measurements of the signal-to-noise ratio and the response as a function of the position of the sensor are presented. A deconvolution method is successfully applied, and a comparison of the measured shower shape as a function of the absorber depth with a Monte-Carlo simulation is given.

The VELO Upgrade

A significant upgrade of the LHCb detector is scheduled to be installed in 2018–2019. Afterwards all sub-detectors will be read out at the LHC bunch crossing frequency of 40 MHz and the trigger will be fully implemented in software. The silicon strip vertex detector will be replaced by a hybrid pixel detector. In these proceedings the following items are discussed: frontend ASIC, data rates, data transmission, cooling, radiation hard sensors, module design and simulated performance.

Low noise 4-channel front end ASIC with on-chip DLL for the upgrade of the LHCb Calorimeter

An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and it incorporates dedicated solutions to achieve low noise, linearity and spill-over specifications. The included DLL is capable of shifting the phase of the LHC clock (25 ns) in steps of 1 ns. The selected technology is AMS SiGe BiCMOS 0.35 um.

Development of the read-out ASIC for muon chambers of the CBM experiment

A front-end ASIC for GEM detectors readout in the CBM experiment is presented. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power comsumption of 10 mW per channel, 6 bit SAR ADC. The chip includes 8 analog processing chains, each consisting of preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consunption at 50 Msps. The chip also includes the threshold DAC and the digital part.

The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data.

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

Prototype of a front-end readout ASIC designed for the Water Cherenkov Detector Array in LHAASO

The Large High Altitude Air Shower Observatory is in the R&D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μ m CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With Time-to-Digital Converters, both time and charge can be digitized at the same time. We have conducted initial tests on this chip, and the results indicate that a time resolution better than 0.5 ns is achieved over the full dynamic range (1 ∼ 4000 photo electrons, corresponding to 0.75 ∼ 3000 pC with the threshold of 0.188 pC); the charge resolution is better than 1% with large input amplitudes (500 ∼ 4000 photo electrons), and remains better than 15% with a 1 photo electron input amplitude, which is beyond the application requirement.

CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

VeloPix: the pixel ASIC for the LHCb upgrade

The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full readout at 40 MHz, with the data fed directly to the software triggering algorithms. The upgraded VELO is a lightweight hybrid pixel detector operating in vacuum in close proximity to the LHC beams.The readout will be provided by a dedicated front-end ASIC, dubbed VeloPix, matched to the LHCb readout requirements and the 55 × 55 μm VELO pixel dimensions. The chip is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s, resulting in a required output bandwidth of more than 16 Gbit/s. The occupancy across the chip is also very non-uniform, and the radiation levels reach an integrated 400 Mrad over the lifetime of the detector.VeloPix is a binary pixel readout chip with a data driven readout, designed in 130 nm CMOS technology. The pixels are combined into groups of 2 × 4 super pixels, enabling a shared logic and a reduction of bandwidth due to combined address and time stamp information. The pixel hits are combined with other simultaneous hits in the same super pixel, time stamped, and immediately driven off-chip. The analog front-end must be sufficiently fast to accurately time stamp the data, with a small enough dead time to minimize data loss in the most occupied regions of the chip. The data is driven off chip with a custom designed high speed serialiser. The current status of the ASIC design, the chip architecture and the simulations will be described.

Recent progress of MPPC-based scintillation detectors in high precision X-ray and gamma-ray imaging

The multi-pixel photon counter (MPPC) is a promising light sensor for various applications, not only in physics experiments but also in nuclear medicine, industry, and even high-energy astrophysics. In this paper, we present the current status and most recent progress of the MPPC-based scintillation detectors, such as (1) a high-precision X-ray and gamma-ray spectral image sensor, (2) next-generation PET detectors with MRI, TOF, and DOI measurement capabilities, and (3) a compact gamma camera for environmental radiation surveys. We first present a new method of fabricating a Ce:GAGG scintillator plate (1 or 2mm thick) with ultra-fine resolution (0.2mm/pixel), cut using a dicing saw to create 50μm wide micro-grooves. When the plate is optically coupled with a large-area MPPC array, excellent spatial resolution of 0.48mm (FWHM) and energy resolution of 14% (FWHM) are obtained for 122keV gamma rays. Hence, the detector can act as a convenient “multi-color” imaging device that can potentially be used for future SPECT and photon-counting CT. We then show a prototype system for a high-resolution MPPC-based PET scanner that can realize ≃1mm (FWHM) spatial resolution, even under a strong magnetic field of 4.7T. We develop a front-end ASIC intended for future TOF-PET scanner with a 16-channel readout that achieves a coincidence time resolution of 489ps (FWHM). A novel design for a module with DOI-measurement capability for gamma rays is also presented by measuring the pulse height ratio of double-sided MPPCs coupled at both ends of scintillation crystal block. Finally, we present the concept of a two-plane Compton camera consisting of Ce:GAGG scintillator arrays coupled with thin MPPC arrays. As a result of the thin and compact features of the MPPC device, the camera not only achieves a small size (14×14×15cm3) and light weight (1.9kg) but also excellent sensitivity, compared to the conventional PMT-based pinhole camera used in Fukushima. Finally, we briefly describe a new product recently developed in conjunction with Hamamatsu Photonics K.K. that offers improved sensitivity and angular resolution of Δθ~8° (FWHM) at 662keV, by incorporating DOI-segmented scintillator arrays.

Development of a multi-channel readout ASIC for a fast neutron spectrometer based on GEM-TPC

A multi-channel front-end ASIC has been developed for a fast neutron spectrometer based on Gas Electron Multiplier (GEM)-Time Projection Chamber (TPC). Charge Amplifier and Shaping Amplifier for GEM (CASAGEM) integrates 16+1 channels: 16 channels for anodes and 1 channel for cathode. The gain and the shaping time are adjustable from 2 to 40 mV/fC and from 20 to 80 ns, respectively. The prototype ASIC is fabricated in 0.35 μm CMOS process. An evaluation Print Circuit Board (PCB) was also developed for chip tests. In total 20 chips have been tested. The integrated nonlinearity is less than 1%. The equivalent noise electrons is less than 2000e when the input capacitor is 50 pF. The time jitter is less than 1 ns. The design and the test results are presented in the paper.

Development of a current-mode ASIC for MRPC detectors

A fully current-mode front-end ASIC, named CAD has been developed for MRPC detectors for TOF applications. It consists of a current mirror preamplifier and a current discriminator for each channel. Current mode circuits can easily achieve high bandwidth and are suitable for low power supply design. A simplified circuit model has been introduced to analyze the timing performance of the current discriminator. 20 ps time jitter can be achieved for 40 fC input signal by simulation. The time jitter dramatically decreases as signal amplitude increases. A 4-channel prototype ASIC has also been designed and fabricated in a 0.35 μm CMOS technology. The chip has been evaluated with MRPC detector. The total time jitter of 184 ps has been measured.

Reduction of silicon photomultipliers thermal generation in self-coincidence system applied in low level light measurements

Abstract The paper presents method for thermal generation reduction in low level light applications, especially where measured phenomena have random character. The algorithm was developed basing on cosmic ray measurements. The main parts of the system are: Silicon Photomultipliers (SiPM), front-end ASIC for amplifying and shaping signals. SiPM is a very sensitive device which can detect single photons. Comparing to a standard photomultiplier SiPM has a compact size, low operating voltage and it is immune to an electromagnetic field. Thermally generated signals are disadvantage of SiPM. This paper presents the measurement method to reduce influence of thermal generation.

Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3mm2 in size with a Pico-second Light Pulsar with a light emission peak of 655nm and pulse duration of 54ps (FWHM). We obtained 105ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array.

Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ~500 e− and a noise slope of ~5 e−/pF (r.m.s.) with a power consumption of 2.1mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ~12keV (FWHM) at 662keV and ~24keV (FWHM) at 1.33MeV.

Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

The higher luminosity that is expected for the LHC after future upgrades will require better performance by the data acquisition system, especially in terms of throughput. In particular, during the first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector will be equipped with a fourth layer – the Insertable B-Layer or IBL – located at a radius smaller than the present three layers. Consequently, a new front end ASIC (FE-I4) was designed as well as a new off-detector chain. The latter is composed mainly of two 9U-VME cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Actual production of another 15 ROD cards is ongoing in Fall 2013, and commissioning is scheduled in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards will be produced for a total of 20 boards. This paper describes some integration tests that were performed and our plan to test the production of the ROD cards. Slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. This contribution will report also one view on the possible adoption of the IBL ROD for ATLAS Pixel Detector Layer 2 (firstly) and, possibly, in the future, for Layer 1.

Characterization of a module with pixelated CdTe detectors for possible PET, PEM and compton camera applications

We present the measurement of the energy resolution and the impact of charge sharing for a pixel CdTe detector. This detector will be used in a novel conceptual design for diagnostic systems in the field of nuclear medicine such as positron emission tomography (PET), positron emission mammography (PEM) and Compton camera. The detector dimensions are 10 mm × 10 mm × 2 mm and with a pixel pitch of 1 mm × 1 mm. The pixel CdTe detector is a Schottky diode and it was tested at a bias of -1000 V. The VATAGP7.1 frontend ASIC was used for the readout of the pixel detector and the corresponding single channel electronic noise was found to be σ < 2 keV for all the pixels. We have achieved an energy resolution, FWHM/Epeak, of 7.1%, 4.5% and 0.98% for 59.5, 122 and 511 keV respectively.The study of the charge sharing shows that 16% of the events deposit part of their energy in the adjacent pixel.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10bit resolution, 50–100MHz conversion frequency and less than 1mW power consumption are the today׳s standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC׳s and TDC׳s developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.