Front-end ASIC Research Articles

The CGEM-IT readout chain

An innovative Cylindrical Gas Electron Multiplier (CGEM) detector is under construction for the upgrade of the inner tracker of the BESIII experiment. A novel system has been worked out for the readout of the CGEM detector, including a new ASIC, dubbed TIGER -Torino Integrated GEM Electronics for Readout, designed for the amplification and digitization of the CGEM output signals. The data output by TIGER are collected and processed by a first FPGA-based module, GEM Read Out Card, in charge of configuration and control of the front-end ASICs. A second FPGA-based module, named GEM Data Concentrator, builds the trigger selected event packets containing the data and stores them via the main BESIII data acquisition system. The design of the electronics chain, including the power and signal distribution, will be presented together with its performance.

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a custom-designed chip to receive the Address in Real Time (ART) signals from the VMM front-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. After four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

GBTX Emulation for BM@N/MPD Data Acquisition Systems

The GBTX chip is widely used in high-energy experiments. However, due to export restrictions, it cannot be used in NICA. There is significant synergy in building readout chains for CBM and NICA experiments. To fully utilize this synergy, it is important to emulate the essential GBTX functionality in FPGA. For that purpose, the emulator of GBTX (GBTx- EMU) has been developed. The GBTxEMU may be implemented in cheap FPGAs, including Artix-7, and enables creating multichannel data acquisition chains based on the same front-end ASICs (SMX2 developed at AGH) as the one used in CBM. The GBTxEMU may work with the DPB boards developed for CBM, but a dedicated, price-optimized solution is under development.

An Optimized Radiation Tolerant Baseline Correction Filter for HEP Using AI Methodologies

This paper presents an improved baseline correction filter to be used in the readout front-end ASICs of gaseous detector systems in high energy physics experiments. The digital filter is based on an FIR section and used in the data pipeline running in real-time thought the input signals, allowing adequate data compression by the subsequent blocks in the processing chain. The proposed design was optimized to cope with the power and area trade-offs while hardening the block using redundancy and a novel automated design system based on artificial intelligence. This optimizer is also discussed including its logic and improvements using genetic algorithms with dynamic mutation and cross-over probabilities connected to run-time EDA tools. The designed filter was fabricated in 130 nm process, packaged and tested in the Peletron particle accelerator at the University of Sao Paulo. The device was irradiated and received a total dose of 70 krad during about one week of exposition to alpha particles without any measured failure, validating the design and solving the vulnerability with a small increase in the channel area of just 0.07%.

ATLAS ITk pixel endcap demonstrator “Ring-0” construction and testing

The ATLAS upgrade programme for the High-Luminosity Large Hadron Collider (HL-LHC) includes the replacement of the inner tracking detector with an all-silicon Inner Tracker system (ITk). The outer layers of the new tracker consist of strip sensors and the inner region is made up of pixel sensors. This paper describes the development of the endcaps for the pixel system. The endcaps are built from half-rings, carrying the pixel modules and the services. A prototype half-ring populated with pixel modules, read out using FEI4 front-end ASICs in a serial powering chain, was constructed. The half-ring’s mechanical and electrical structure and the assembly process are described. The electrical measurements of the modules are presented, focusing on their performance in the serial powering chain.

Development of a low-noise front-end ASIC for CdTe detectors

We present our latest ASIC, which is used for the readout of Cadmium Telluride double-sided strip detectors (CdTe DSDs) and high spectroscopic imaging. It is implemented in a 0.35 μm CMOS technology (X-Fab XH035), consists of 64 readout channels and has a function that performs simultaneous AD conversion for each channel. The equivalent noise charge of 54.9e−± 11.3e− (rms) is measured without connecting the ASIC to any detectors. From the spectroscopy measurements using a CdTe single-sided strip detector, the energy resolution of 1.12 keV (FWHM) is obtained at 13.9 keV, and photons within the energy from 6.4 keV to 122.1 keV are detected. Based on the experimental results, we propose a new low-noise readout architecture making use of a slew-rate limited mode at the shaper followed by a peak detector circuit.

Single Event Upset rates in the CBC in CMS

The CMS Binary Chip (CBC) is a front-end ASIC to be used by the CMS tracker following its upgrade for High Luminosity LHC operation. It will instrument special silicon microstrip detectors to identify high transverse momentum particles in real time so tracking data can be used in the L1 trigger. The CBC should be robust against Single Event Upsets (SEUs). SEU rates have been measured in a series of tests in a 62 MeV proton beam. Each version of the chip has increased the digital circuitry, and hence the SEU susceptibility, and has also been subject to design improvements which affect SEU tolerance. The relevant design features are explained and SEU measurements reported. The expected SEU rates at the HL-LHC are estimated.

Performance of a Front End prototype ASIC for picosecond precision time measurements with LGAD sensors

For the High-Luminosity phase of LHC, the ATLAS experiment is proposing the addition of a High Granularity Timing Detector (HGTD) in the forward region, to mitigate the effects of the increased pile-up. The chosen detection technology is Low Gain Avalanche Detector (LGAD) silicon sensors that can provide an excellent timing resolution below 50 ps. The front-end read-out ASIC must exploit the large signal derivative and small noise provided by the sensor, while keeping low power consumption. This paper presents the results on the first prototype of a front-end ASIC, named ALTIROC0, which contains the analog stages (preamplifier and discriminator) of the read-out chip. The ASIC was characterised both alone and as part of a module with a 2×2 LGAD array of 1.1×1.1 mm2 pads bump-bonded to it. The various contributions of the electronics to the time resolution were investigated in test-bench measurements with a calibration setup. Both when the ASIC is alone or with a bump-bonded sensor, the jitter of the ASIC is better than 20 ps for an injected charge of 10 fC . The time walk effect, which arises from the different preamplifier response for various injected charges, can be corrected up to 10 ps using a Time Over Threshold measurement. The combined performance of the ASIC and the LGAD sensor, which was measured during a beam test campaign in October 2018 with pions of 120 GeV energy at the CERN SPS, is around 40 ps for all measured modules. All tested modules show good efficiency and time resolution uniformity.

A multichannel front-end readout ASIC for picosecond time resolution systems based on thin UFSD

This work presents FAST, a multichannel readout ASIC designed to measure the time of arrival of MIP particles in Ultra-Fast Silicon Detectors (UFSD) with a time resolution of about 30 ps. The FAST ASIC is oriented to future High Energy Physics experiments, where high time resolution is exploited to mitigate pile-up effects, and more generally, to those applications that require accurate Time-of-Flight Silicon systems with low power consumption. The prototype has been designed in 110 nm CMOS technology, in three different flavors of front-end architecture. Each flavor is implemented in a different 20-channel ASIC. For all flavors, the power consumption of the front-end is 1.2 mW/channel. The three flavors of FAST are described in the paper, together with the simulation showing the timing performance of FAST coupled to different sensors geometries.

Development of a silicon microstrip detector prototype for ultra-fast imaging at a synchrotron radiation beam

A method of imaging of ultra-fast processes, like explosion or fast combustion, at a synchrotron radiation beam is being developed at the Siberian Synchrotron and Teraherz Radiation Center (SSTRC) . Two stations are operating at beam line 0 at the VEPP-3 storage ring and at beam line 8 at the VEPP-4M storage ring. Both stations are equipped with the detector for imaging of explosions DIMEX, based on high pressure ionization chamber, and allowing to record up to 100 one dimensional images with the frame rate of 8 MHz. However the maximum flux that DIMEX can detect is limited as well as spatial resolution and frame rate because of gas technology used. In view of significant increase of SR flux at the VEPP-4M beam line due to the new 9-pole 2 T wiggler, a new detector is being developed for this beam line, based on Si microstrip sensor. The first Si microstrip detector prototype has been mounted with new specially developed front-end ASIC that allows to record data with the rate of 50 MFrames/s. The first measurements with this prototype demonstrated significant improvement of all critical parameters of the detector compared to the gaseous version.

WASA: a low power front-end ASIC for time projection chambers in 65 nm CMOS

A low power front-end ASIC, named WASA has been developed for the time projection chamber for the CEPC (Circular Electron Positron Collider) experiment. Power consumption becomes very critical and is addressed by using 65 nm CMOS process and circuit structure with simple analog circuits. Three prototype ASIC chips have been designed and fabricated, including the 5-channel analog front-end (AFE) chip, the SAR ADC chip and the mixed-signal chip with the AFE and the ADC together. Only the design and the test results of the AFE and the SAR ADC chips are reported in this paper. The power consumptions of the AFE and the SAR ADC core were measured to be 2.0 mW and 1.0 mW per channel respectively. The gain and the ENC noise of the AFE were 8.91 mV/fC and 644 electrons @ 10 pF input capacitance, including the contribution of 460 electrons from the external buffer for test purpose. The INL was less than 0.5% for a dynamic range of 145 fC. The maximum crosstalk between two adjacent channels was 0.39%. The SNDR and SFDR of ADC were measured to be 57.2 dB and 79.4 dBc at 50 MS/s for a 2.4 MHz input sine signal, corresponding to an ENOB of {9.2} bit. The total ionizing dose (TID) tests were also done for the AFE and the SAR ADC. No significant performance degradation {was} observed for the total dose up to 1 Mrad (Si).

The FELIX detector interface for the ATLAS TDAQ upgrades and its deployment in the ITk demonstrator setup

The ATLAS experiment at the LHC at CERN will move to use the Front-End Link eXchange (FELIX) system in a staged approach for LHC Run 3 (2021) and LHC Run 4 (2026). FELIX will act as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. FELIX functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run innovative multi-threaded software for event fragment building, processing, buffering and forwarding. This proceeding will describe the design and status of the FELIX based readout for the Run 3 upgrade, during which a subset of the detector will be migrated. It will also show how the same concept has been successfully introduced into the demonstrator test bench of the ATLAS Pixel Inner Tracker, acting as a proof of concept towards the longer term Run 4 upgrade in which all detectors will adopt a FELIX based readout.

Performance study of HGCROC-v2: the front-end electronics for the CMS High Granularity Calorimeter

The High Granularity Calorimeter (HGCAL), presently being designed by the Compact Muon Solenoid collaboration (CMS) to replace the existing endcap calorimeters for the High Luminosity phase of the LHC (HL-LHC), will feature unprecedented transverse and longitudinal readout and triggering segmentation for both electromagnetic and hadronic sections. The requirements for the front-end electronics are extremely challenging, including high dynamic range (0–10 pC), low noise (0∼ 200 electrons), high-precision timing information in order to mitigate the pileup effect (25 ps binning) and low power consumption (∼ 15 mW/channel). The front-end electronics will face a harsh radiation environment which will reach 200 Mrad at the end of life. It will work at a controlled temperature of 240 K. HGCROC-v2 is the second prototype of the front-end ASIC. It has 72 channels of the full analog chain: low noise and high gain preamplifier and shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range of the preamplifier, a discriminator and TDC provide the charge information from TOT (Time Over Threshold) over 200 ns dynamic range using 50 ps binning. A fast discriminator and TDC provide timing information to 25 ps accuracy. Both charge and timing information are kept in a DRAM memory waiting for a Level 1-trigger decision (L1A). At a bunch crossing rate of 40 MHz, compressed charge data are sent out to participate in the generation of the L1-trigger primitives. We report on the performances of the chip in terms of signal-to-noise ratio, charge and timing, as well as results from radiation qualification with total ionizing dose (TID).

Use of the Peak-Detector mode for gain calibration of SiPM sensors with ASIC CITIROC read-out

The ASIC CITIROC is a 32-channel fully analogue front-end ASIC dedicated to the read-out of silicon photo-multiplier (SiPM) sensors that can be used in a variety of experiments with different applications: nuclear physics, medical imaging, astrophysics, etc. For each channel, two parallel AC coupled voltage preamplifiers, one for the high gain and one for the low gain, ensure the read-out of the charge from 160 fC to 320 pC (i.e. from 1 to 2000 photo-electrons with SiPM gain = 106, with a photo-electron to noise ratio of 10). The signal in each of the two preamplifier chains is shaped and the maximum value is captured by activating the peak detector for an adjustable time interval. In this work, we illustrate the peak detector operation mode and, in particular, how this can be used to calibrate the SiPM gain without the need of external light sources. To demonstrate the validity of the method, we also present and discuss some laboratory measurements.

A TDM-Based 16-Channel AFE ASIC With Enhanced System-Level CMRR for Wearable EEG Recording With Dry Electrodes.

A multi-channel analog front-end (AFE) ASIC for wearable EEG recording application is presented in this article. Two techniques, namely chopping stabilization (CS) and time-division-multiplexing (TDM) are combined in a unified manner to improve the input-referred noise and the system level common-mode rejection ratio (CMRR) for multi-channel AFE. With the proposed TDM/CS structure, multiple channels can share single second-stage amplifier for significant reduction in chip size and power consumption. Dual feedback loops for input impedance boosting as well as electrode offset cancellation are incorporated in the system. Implemented in a 0.18-μm CMOS process, the AFE consumes 24 μW under 1 V supply. The input referred noise is 0.63 μVrms in 0.5Hz-100Hz and the input impedance is boosted to 560 MΩ at 50Hz. The measured amplifier intrinsic CMRR and system-level AFE CMRR are 89 dB and 82 dB, respectively.

Characterization of a newly developed readout electronics system for strip detectors

The aim of the present paper was to investigate the performance of a newly developed general purpose strip detector system, and its energy resolution improvement provided by custom characterization and calibration procedures described in this paper. The system contains one 128-channel silicon strip detector, four 32-channel Front-End ASICs (FE-ASICs), FPGA-based control circuit, and signal conditioning and power regulation modules, providing energy measurements up to 3.2 MeV per channel. Additionally, a dedicated software tool was developed to control and configure the system, as well as, to automatically characterize and equalize the channels aiming a more uniform response and hence, better energy resolution. It is worth noting that a sigma of 1.6 keV has been achieved for all 128 channels within the lower range of the ASIC (up to 800 keV), while the ASICs were not optimized to work with the specific detector capacitance. This energy resolution is comparable to state of the art Si hybrid-pixel detector Timepix3 [1]. Using a conservative 6-sigma distance to the electronic noise level it was still obtained a system threshold level of 3 keV . This work provides valuable information for particular applications in which a general purpose strip detector-based system could be used efficiently to replace hybrid pixel detectors.

Beam test performance of prototype silicon detectors for the Outer Tracker for the Phase-2 Upgrade of CMS

A new CMS tracker detector will be installed for operation at the High Luminosity LHC (HL-LHC). This detector comprises modules with two closely spaced parallel sensor plates and front-end ASICs capable of transmitting tracking information to the CMS Level-1 (L1) trigger at the 40 MHz beam crossing rate. The inclusion of tracking information in the L1 trigger decision will be essential for selecting events of interest efficiently at the HL-LHC. The CMS Binary Chip (CBC) has been designed to read out and correlate hits from pairs of tracker sensors, forming so-called track stubs. For the first time, a prototype irradiated module and a full-sized module, both equipped with the version 2 of the CBC, have been operated in test beam facilities. The efficiency of the stub finding logic of the modules for various angles of incidence has been studied. The ability of the modules to reject tracks with transverse momentum less than 2 GeV has been demonstrated. For modules built with irradiated sensors, no significant drop in the stub finding performance has been observed. Results from the beam tests are described in this paper.

Phase I Upgrade of the Readout System of the Vertex Detector at the LHCb Experiment

This article describes the high-speed system designed to meet the challenging requirements for the readout of the new pixel VErtex LOcator (VELO) of the upgraded LHCb experiment. All elements of the electronics readout chain will be renewed to cope with the requirement of ~40-MHz full-event readout rate. The pixel sensors will be equipped with VeloPix ASICs and placed at ~5 mm from the Large Hadron Collider (LHC) beams in a secondary vacuum tank in an extremely high and nonhomogeneous radiation environment. The front-end (FE) ASICs with the highest occupancy will have to cope with pixel-hit rates above ~900 Mhits/s using up to four 5.13-Gb/s data readout links. Each module comprises six VeloPix ASICs, wire-bonded to two FE hybrid boards, while a third hybrid will employ a GBTx ASIC as the control interface. High-speed data will reach the wall of the vacuum chamber through low-mass flexible copper tapes. A custom board routes the signals outside the vacuum tank. On the air side, an optical and power board converts the electrical high-speed signals into optical signals for transmission from the underground cavern to the off-detector electronics that process data and send them to a farm of computers for further analysis. Several tests allowing the validation of the system are described here with special emphasis on a test with proton beams that confirms the correct operation of the whole readout hardware.

FELIX: the new detector interface for ATLAS

After the current LHC shutdown (2019-2021), the ATLAS experiment will be required to operate in an increasingly harsh collision environment. To maintain physics performance, the ATLAS experiment will undergo a series of upgrades during the shutdown. A key goal of this upgrade is to improve the capacity and flexibility of the detector readout system. To this end, the FrontEnd Link eXchange (FELIX) system has been developed. FELIX acts as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. The system functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. The serial links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunchcrossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. FELIX uses commodity server technology in combination with FPGA-based PCIe I/O cards. FELIX servers run a software routing platform serving data to network clients. Commodity servers, connected to FELIX systems via the same network, run the new multi-threaded Software Readout Driver (SW ROD) infrastructure for event fragment building, buffering and detector-specific processing to facilitate online selection. This presentation will cover the design of FELIX and the results of the installation and commissioning activities for the full system.

Single event upsets in the ATLAS IBL frontend ASICs at the Large Hadron Collider at CERN

ATLAS is one of the four major experiments at the Large Hadron Collider at CERN. The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel detector, located at the core the ATLAS tracker. During operation at instantaneous luminosities of up to 2.1 × 1034 cm−2 s−1 the frontend chips of the ATLAS innermost pixel layer experienced single event upsets affecting their global registers as well as the settings for the individual pixels, causing, amongst other things, loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques are presented.