Abstract
The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.
Highlights
The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems
The SCA is broadly composed of two e-link ports that connect to the GBTX ASICs, a set of user interface ports to connect with the ondetector electronics and a network controller that routes the information between the e-links and the user interfaces
The SCA ASIC connects via an e-link to the special purpose slow control e-port of the GBTX ASIC
Summary
The architecture of the SCA ASIC is shown in figure 4. This dedicated e-port runs at 40MHz double date rate (DDR) mode giving an effective data rate of 80 Mbps. On power-up the primary e-port is automatically selected for operation Both e-ports communicate with the Network Controller block via an Atlantic interface parallel bus [4]. The I2C channels feature individually programmable data transfer rates from 100KHz to 1MHz and can generate both 7-bit and 10-bit address as well as single-byte and multi-byte I2C bus transactions. The JTAG channel is implemented around two 128-bit shift register that serializes and deserializes the bit-streams between the TMS, TDO and TDI lines and the internal parallel bus. There are four independent digital to analog converter (DAC) channels featuring 8-bit resolution and capable to generate voltage signals in the range of 0.0 V to 1.0 V
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