Front-end ASIC Research Articles

TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

A front end ASIC for the readout of the PMT in the KM3NeT detector

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I2C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

The frontend electronics for the LHCb upgrade

The LHCb detector is optimized for the measurement of b-physics at the LHC. The current detector is complete and taking data at its design luminosity 2 × 1032cm−2s−1. An upgrade program has started to operate the detector at a 10 fold increased luminosity from 2017 onwards. A new readout architecture is proposed in which all detector data are transmitted at every LHC bunch-crossing from the frontend to a large farm of CPUs where complex and flexible event filter algorithms will be implemented. This implies that all sub-detectors have to adapt or rebuild their front-end electronics to zero suppress and transmit data at 40MHz. Some sub-detectors need new front-end ASICs, but others consider the use of radiation tolerant commercial FPGAs.

The ATLAS silicon microstrip tracker. Operation and performance

In December 2009 the ATLAS experiment at the CERN Large Hadron Collider (LHC) recorded the first proton-proton collisions at a centre-of-mass energy of 900 GeV. This was followed by collisions at the unprecedented energy of 7 TeV in March 2010. The SemiConductor Tracker (SCT) is a precision tracking device in ATLAS made up from silicon microstrip detectors processed in the planar p-in-n technology. The signal from the strips is processed in the front-end ASICs working in binary readout mode. Data is transferred to the off-detector readout electronics via optical fibers. The completed SCT has been installed inside the ATLAS experiment. Since then the detector was operated for two years under realistic conditions. Calibration data has been taken and analysed to determine the performance of the system. In addition, extensive commissioning with cosmic ray events has been performed both with and without magnetic field. The sensor behaviour in magnetic field was studied by measurements of the Lorentz angle. After this commissioning phase it arrived to the first LHC pp collision runs in very good shape: 99% of the SCT strips are operational, noise occupancy and hit efficiency exceed the design specifications, the alignment is already close enough to the ideal one to allow online track reconstruction and invariant mass determination.

Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs

A new SEU-robust D-flip-flop register structure was designed in 130 nm CMOS for implementation of front-end detector ASICs. The register was tested in a heavy ion beam facility and showed a cross section lower than 10−10 cm2/bit in the LET range 1.2–62.0 MeVcm2/mg, representing an improvement of more than 103 times over previously studied standard library cells. No errors at all were observed at LETs below 30 MeVcm2/mg.

Digital part of PARISROC2: a photomultiplier array readout chip

PARISROC is the front-end ASIC designed to read 16photomultiplier (PM) tubes for neutrino experiments. It's able toshape, discriminate, convert and readout data in an autonomous andchannel-independent mode. The tests made on PARISROC1 have shown somelimitations on time measurements and on hit rate capability. In orderto correct these points, the digital part of PARISROC2 has beencompletely modified to add new features and improvements. First, itintegrates a new time to amplitude converter with less than 1 nsresolution. Secondly, conversion and readout has been speeded-up by afactor of 4 to handle the PM hit rate. The chip was received inFebruary 2010.

Low-Noise Analog ASIC for Silicon and CdTe Sensors

We report on the recent development of a 32-channel low-noise analog front-end ASIC "KW03" for hard X-ray and gamma-ray detectors. The ASIC aims for the readout of strip or pixel (pad) detectors utilizing silicon and cadmium telluride (CdTe) as detector materials. Each readout channel includes a charge-sensitive amplifier, bandpass filters and a sample-and-hold circuit. It also includes a leakage current compensation and pole-zero cancellation circuits to meet the various detector requirements. The equivalent noise level of a typical channel reaches 89 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> @ 0 pF (rms) and shows an input-capacitance characteristic of 7.5 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> /pF between 0 pF and 10 pF with a power consumption of 3 mW per channel. We mounted the ASIC on a low-temperature co-fired ceramic (LTCC) package and evaluated the spectral performance by combining with a CdTe diode detector. As a result, the gamma-ray spectrum of radioactive source 241 Am was obtained with a good energy resolution of 2.23 keV (FWHM) for gamma rays of 59.5 keV at -20°C.

Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 ×32 pixels covering about 1 cm 2 active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280 μ m × 280 μ m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4×4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

Performance of the front-end electronics of the ANTARES neutrino telescope

ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

Design and characterization of a multi-channel front-end readout ASIC with low noise and large dynamic input range for APD-based PET imaging

This paper represents the design of a low-noise, wide band multi-channel readout integrated circuit (IC) used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The first 10-channel prototype chip (APD_Chip) of the analog parts has been designed and fabricated in a 0.35-μm CMOS process. Every channel of the APD_Chip includes a charge-sensitive preamplifier (CSA), a CR-(RC)2 shaper, and an analog buffer. In each channel, the CSA reads charge signals (10 bits dynamic range) from an APD array having 10 pF of capacitance per pixel. A linearized degenerated differential pair which ensures high linearity in all dynamical range is used as the high feedback resistor for preventing pile up of signals. The designed CSA has the capability of compensating automatically up to 200 nA leakage current from the detector. The CR-(RC)2 shaper filters and shapes the output signal of the CSA. An equivalent input noise charge obtained from test is 275 e? + 10 e?/pF. In this paper the prototype is presented for both its circuits design and its test results.

Development of an SOI analog front-end ASIC for X-ray charge coupled devices

The FD-SOI technology is a fascinating LSI fabrication process as a possible radiation-tolerant device. In order to confirm benefits of the FD-SOI and expand application ranges in front-end electronics, we experimentally designed an analog front-end ASIC for X-ray CCD readout with the FD-SOI process. The circuit design was submitted to OKI Semiconductor Co., Ltd. via the multi-chip project as a part of the SOI pixel-detector R&D program in KEK. The ASIC contains seven readout channels using the correlated double sampling technique, and includes key circuit elements for a low-noise LSI. This paper describes the circuit design and the performance of the ASIC together with the radiation tolerance.

Development of a front end ASIC for Dark Matter directional detection with MIMAC

A front end ASIC (BiCMOS-SiGe 0.35 μ m ) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous μ TPC . The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2×96 strips of pixels are monitored.

Novel Front-End Pulse Processing Scheme for PET System Based on Pulse Width Modulation and Pulse Train Method

The architecture of a multi-channel front-end system is important for realizing a high-resolution PET system. We propose a novel front-end pulse processing scheme with pulse width modulation (PWM) and pulse train method for PET systems. Each channel of the proposed system consists of a preamplifier, a shaping amplifier, a comparator, and a digital circuit that generates a pulse train for each event. The preamplifier-shaper-discriminator module first generates a trigger pulse with time-over-threshold (ToT), which contains the energy information. The trigger pulse is then processed through a digital circuit that adds subsequent pulses to form a pulse train. These additional pulses encode channel information, timing information, etc. The digital signal output of each channel can be connected by simple wired-OR logic, and the output is read in one transmission line. This multi-channel, low power consumption front-end scheme can acquire enough pulse height (energy) and position information to realize a PET system with a significantly smaller number of output pins in the front-end ASIC. The pulse width encoding also simplifies the digital processing system. We designed a new ASIC based on this concept. The proposed architecture can be applied to high-resolution PET systems with multi-channel ASICs.

PARISROC, a photomultiplier array readout chip (PMm2 collaboration)

PARISROC is a complete readout chip, in AMS SiGe 0.35μm technology, for photomultipliers array. It is a front-end electronics ASIC which allows trigerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French National Agency for Research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerless acquisition and only sends out the relevant data by network to the central data storage. This data management reduces considerably the cost of these detectors. This paper describes the front-end electronics ASIC called PARISROC which integrates totally independents 16 channels with a variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.

Imaging detector development for nuclear astrophysics using pixelated CdTe

The concept of focusing telescopes in the energy range of lines of astrophysical interest (i.e., of energies around 1MeV) should allow to reach unprecedented sensitivities, essential to perform detailed studies of cosmic explosions and cosmic accelerators. Our research and development activities aim to study a detector suited for the focal plane of a γ-ray telescope mission. A CdTe/CdZnTe detector operating at room temperature, that combines high detection efficiency with good spatial and spectral resolution is being studied in recent years as a focal plane detector, with the interesting option of also operating as a Compton telescope monitor. We present the current status of the design and development of a γ-ray imaging spectrometer in the MeV range, for nuclear astrophysics, consisting of a stack of CdTe pixel detectors with increasing thicknesses. We have developed an initial prototype based on CdTe ohmic detector. The detector has 11×11 pixels, with a pixel pitch of 1mm and a thickness of 2mm. Each pixel is stud bonded to a fanout board and routed to an front end ASIC to measure pulse height and rise time information for each incident γ-ray photon. First measurements of a 133Ba and 241Am source are reported here.

Hard X-ray and gamma-ray detector for ASTRO-H based on Si and CdTe imaging sensors

We have been developing a hard X-ray imager and soft gamma-ray detector as on board instruments of the ASTRO-H mission. The Hard X-ray Imager (HXI) is one of the three focal plane detectors of ASTRO-H, which is aimed to realize the focusing imaging of hard X-ray photons in combination with hard X-ray telescopes. By use of the hybrid structure composed of double-sided silicon strip detectors and a cadmium telluride strip detector, it fully covers the energy range up to 80keV with a high quantum efficiency. High spatial resolutions of 250μm pitch and energy resolutions of 1–2keV (FWMH) are at the same time achieved with low noise front-end ASICs. The Soft Gamma-ray Detector (SGD) is a novel and unique detector which is characterized by semiconductor Compton cameras surrounded by narrow field-of-view active shields, and covers a higher energy range (30–600keV) than that of HXI. It consists of four Compton Cameras constructed with many layers of Silicon and CdTe pad detectors. With its multi-layer structure and Compton reconstruction capability, in addition to the BGO active shields read by Avalanche photo-diodes, this detector will achieve an extremely high background rejection efficiency in the orbit. We report the current status of hardware development including the design requirement, expected performance, and technical readinesses of key technologies.

First Readout of a 64 $\times$ 64 DEPFET Matrix With VELA Circuit

The new advancements in low-noise X-Ray detection pave the way to new space missions for deep space investigation like IXO. The concept of APS (Active Pixel Sensor) devices based on DEPFET (Depleted P-channel FET) structure has been developed to cope with the emerging requirements of low noise and high readout speed. Although the use of DEPFET makes achievable the required noise performance, it is necessary to develop a suitable front-end ASIC to fulfill the challenging speed requirements. We have developed VELA, a new fast multi-channel ASIC for the readout of a DEPFET matrix at high frame rate. The implemented circuit operates the DEPFET pixels in a drain current configuration to achieve a readout speed of 2 ?s per line or even faster. The current version of VELA integrates 64 analog channels to readout a 64 × 64 DEPFET matrix up to 7800 frames per second. In the paper, the circuit and the working principle are presented; the VELA performance and the first measurement with a 64 × 64 DEPFET matrix are also reported.

A multi-channel readout electronics system for GEM and MICROMEGAS

A multi-channel readout electronics system for GEM and MICROMEGAS has been developed. It consists of a front-end ASIC, a multi-channel ADC and a FPGA to sample the signal waveforms in real time. The gain of the front-end ASIC can be programmable from 1 mV/fC to 19 mV/fC and the output pulse width can be adjusted from 200 ns to 800 ns. The ENC is measured to be below 2000 e for Cin < 20 pF and below 5000 e for Cin < 60 pF. Detailed circuit performance and test results with detectors will be described in this paper.

VELA: A fast DEPFET readout circuit for the IXO mission

The concept of active pixel sensor based on depleted P-channel FET (DEPFET) has been developed to cope with the emerging requirements of low noise and speed. The DEPFET detector/amplifier [1], thanks to an intrinsic low anode capacitance, can provide excellent energy resolution and fast readout at the same time. However, in order to fully exploit the speed capability, it is necessary to develop a new readout electronics, which is different from the ones employed up to now. For this purpose, we have developed a new front-end ASIC, named VLSI Electronic for Astronomy (VELA). The implemented circuit operates the pixels in a new current readout configuration to implement an extremely fast readout. The current version of VELA reads out 64×64 DEPFET matrixes with unparalleled frame rate and excellent energy resolution. The circuit architecture, the working principle, and the VELA suitability for X-ray imaging will be shown.

The ECAL online software in the commissioning of the CMS detector

The Electromagnetic Calorimeter (ECAL) of the Compact Muon Solenoid (CMS) detector at the CERN Large Hadron Collider (LHC) is a crystal homogeneous calorimeter made of about 76 000 lead tungstate crystals. The detector was installed in the CMS experimental cavern in 2007 and 2008 and was commissioned with cosmic rays and with LHC beams in 2008. The trigger and data acquisition system of the CMS ECAL comprises 35 000 Front End ASICs and 170 Off Detector VME Boards. The operation of the system, performed by the ECAL online software, requires the configuration of O ( 10 7 ) parameters and the realtime monitoring of O ( 10 5 ) registers. In this paper we discuss the design and architecture of the ECAL online software and its performances in cosmic ray runs and with the first LHC beams.