Abstract
A significant upgrade of the LHCb detector is scheduled to be installed in 2018–2019. Afterwards all sub-detectors will be read out at the LHC bunch crossing frequency of 40 MHz and the trigger will be fully implemented in software. The silicon strip vertex detector will be replaced by a hybrid pixel detector. In these proceedings the following items are discussed: frontend ASIC, data rates, data transmission, cooling, radiation hard sensors, module design and simulated performance.
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