Fractional Spurs Research Articles

Linearised charge pump independent of current mismatch through timing rearrangement

In conventional fractional N phase-locked loops (PLLs), charge pump nonlinearity dominates the overall loop linearity. A nonlinear charge pump increases close-in phase noise and fractional spur. Charge pump nonlinearity is mainly caused by up and down current mismatch which is in turn caused by device mismatch, and finite output impedance. A new charge pump linearisation technique is proposed by introducing an extra delay in the phase-frequency detector (PFD), so that charge nonlinearity caused by current mismatch is cancelled. The new method is independent of current mismatch. A fractional N PLL has been implemented in a 0.18 µm CMOS technology with the proposed linearisation technique. The measured fractional spur at 300 kHz offset is −77 dBc at 3.975 GHz.

A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS

This paper presents a fractional frequency divider-by-1.25 and associated all-digital calibration circuitry. The divider can be used in a wireless transceiver to prevent direct or harmonic pulling of the VCO by the power amplifier. Timing errors between the quadrature phases used in the phase-rotating divider introduce fractional spurs at the output. In this design, the timing errors are measured with a stochastic time-to-digital converter with 20 fs resolution, and corrected to suppress output spurs. The fractional divider has been implemented in a 45 nm CMOS LP process and its core dissipates an estimated 17 mA current from a 1.1 V supply. After calibration, fractional spurs are on average below -59 dBc and -50 dBc (¿ ~ 2 dB over 10 samples) with a 2.5 and 3.8 GHz output frequency respectively. Calibration performance has been confirmed for temperatures from -20°C up to 85°C. The low spur level facilitates radio co-existence with no need for additional filtering. This makes this divider a good candidate for WiFi and WiMAX radios up to 3.8 GHz.

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

The fundamentals and state of the art in fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked-loop (PLL)-based frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLLs and quantization noise and fractional spur suppression techniques for wide-bandwidth applications.

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 mus. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under - 75 dBc. The phase noise at 400 kHz and 3 MHz are -115.6 dBc/Hz and -134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 mu m CMOS process, and occupies an active area of 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.

DWA TECHNIQUE TO IMPROVE DAC OF SIGMA-DELTA FRACTIONAL-N FREQUENCY SYNTHESIZER FOR WIMAX

A first order of DWA (Data Weighted Averaging) algorithm with third order sigma-delta modulator is proposed for application in sigma-delta fractional-N frequency synthesizer for WiMAX. In addition, this paper discusses the impact of mismatch between Digital-to-Analog convertor (DAC) unit elements. The simulation results show the effectiveness of the DWA technique in reduction of spurs, also DWA technique proves its ability to solve DAC unit elements mismatch. The fractional spur noise is converted into a broadband. Quantization noise with DWA is improved by – 10 dB if the element mismatch 0.01 and – 5 dB if the element mismatch 0.08 with 8 bit PFD/DAC. Matlab (V.7) program is used for simulation.

Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-$N$ PLLs

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (??) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ?? fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-?m CMOS process. The fully-integrated ?? fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL can be reduced by replacing the DeltaSigma modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of - 70 dBc and a worst-case in-band fractional spur power of -64 dBc.

Sub-Integer Frequency Synthesis Using Phase-Rotating Frequency Dividers

A generalized architecture and theory for realizing multimodulus, sub-integer frequency division is developed by extending the phase-switched divider technique. The sub-integer divider consists of a pre-scaler, a phase rotator, a post-sealer, and a modulus controller. Phase rotation is proposed as an effective technique to realize fine phase resolution and thereby low sub-integer division ratios, as well as to eliminate the glitch which has plagued phase-switched dividers. Program-swallowed counters are used as the modulus controller to realize a broad-range multimodulus divider. Expressions are derived for the range and resolution of such a program-swallowed, phase-rotating divider. Furthermore, the fractional spurs from this divider topology are derived and related to the linearity of the phase rotator. It is shown that very low (-60 to -75 dBc) fractional spurs at the output of the divider can be attained with reasonably accurate phase rotators. The benefit of this technique is in the ability to realize sub-integer frequency synthesizers which have the architectural simplicity of standard integer- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLLs, but the finer frequency resolution capabilities due to sub-integer division.

A Spur Elimination Technique for Phase Interpolation-Based Fractional-$N$ PLLs

A fractional spur elimination technique that enables wide-bandwidth phase interpolation-based fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loops (PLLs) is proposed. The technique uses specially filtered dither to eliminate the spurious tones otherwise caused by inevitable phase errors. The design of a wide-bandwidth fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL based on the spur elimination technique and a theoretical proof of the proposed technique are presented.

A New Mechanism Producing Discrete Spurious Components in Fractional-$N$ Frequency Synthesizers

Fractional- frequency synthesizers have long been known to suffer from a set of spurious components, often referred to as fractional spurs, which are usually attributed to the operation of the modulator. This paper proposes a new phenomenon-based on cross-coupling and sampling of the nonharmonically related signals present in such synthesizers-which is capable of producing a family of spurious components of identical form to fractional spurs, with support from a range of analytic, simulated and measured results. A unique experimental arrangement is described, allowing controlled cross-coupling of signals within a synthesizer, which provides convincing experimental validation of this mechanism. Finally, techniques are suggested to allow at least partial mitigation of the effect.

A Fractional-&lt;tex&gt;$N$&lt;/tex&gt;Frequency Synthesizer With No Fractional Spurs

The theory, simulation, and experimental verification about a new fractional- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> frequency synthesizer using delta–sigma frequency discriminator are reported. The new synthesizer not only has good performance, but also is suitable for integration. A unique feature also makes it especially useful for phase-array antenna and smart antenna applications.

11 GHz CMOS frequency synthesiser

A fully integrated 11 GHz fractional-N PLL with a three-stage MASH ΣΔ modulator with DC dither in all stages is implemented in a standard 0.13 µm CMOS technology. The synthesiser generates no fractional spurs at frequency offsets outside the loop bandwidth and a small number of fractional spurs with the power not exceeding −44 dBc within the loop bandwidth at the carrier frequency of 11 GHz.

A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications

A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm/sup 2/ PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 /spl mu/s. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing.

A fully integrated fractional-N frequency synthesizer with a wideband VCO and a 3-bit 4th order Σ–Δ modulator for GSM/GPRS/EDGE applications

Abstract A fully integrated fractional-N frequency synthesizer (FNFS) in 0.5 μm SiGe BiCMOS technology is implemented. To cover wideband frequency operation, a switched capacitor bank LC tank VCO and an Adaptive Frequency Calibration (AFC) technique are used. A 3-bit 4th order Σ–Δ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz, and agile switching time. The experimental results show −80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and −129 dBc/Hz out-of-band phase noise at 400 kHz-offset frequency. The fractional spurs are less than −70 dBc/Hz at 300 kHz offset frequency and the reference spur is −75 dBc/Hz. The lock time is less than 150 μs. The proposed synthesizer consumes 19.5 mA from a single 2.8 V supply voltage and meets the requirements of GSM/GPRS/EDGE applications.

Intermodulation-borne fractional-N frequency synthesiser spurious components

Fractional-N frequency synthesisers have long been known to suffer from a set of spurious components, often referred to as ‘fractional spurs’. The authors propose an intermodulation mechanism that is responsible for the production of these components and present numerical and analytic techniques to predict their distribution. These predictions are validated against a range of simulated and measured results to determine the role of intermodulation in fractional-N frequency synthesisers. Finally, two techniques are suggested to allow at least partial mitigation of this effect.

A fractional-N frequency synthesizer architecture utilizing a mismatch compensated PFD/DAC structure for reduced quantization-induced phase noise

Techniques are proposed to dramatically reduce the impact of quantization noise in /spl Sigma//spl Delta/ fractional-N synthesizers, thereby improving the existing tradeoff between phase noise and bandwidth that exists in these systems. The key innovation is the introduction of new techniques to overcome nonidealities in a phase-frequency detector (PFD)/digital-to-analog converter (DAC) structure, which combines the functionality of both phase detector and cancellation DAC into a single element. The proposed architecture achieves better gain matching between the phase-error signal and cancellation DAC than offered by previous approaches. Dynamic element matching techniques are introduced to mitigate the effects of PFD/DAC unit element and timing mismatch on synthesizer phase noise performance. We present behavioral simulations of an example application of this technique that demonstrates 36 dB reduction in broad-band quantization-induced phase noise with the use of a 7-b PFD/DAC. Simulations further demonstrate that fractional spurs are rejected to levels <-90 dBc when a low-cost, low-overhead digital gain correction technique is employed.

A 1.8- GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.

A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800

A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-/spl mu/m CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency.

New spur reduction fractional‐N frequency divider

AbstractA spur reduction technique for fractional‐N frequency synthesis is proposed. This technique can fully suppress the fractional spurs. Furthermore, it provides a simple solution to spur reduction and requires only two 2‐to‐1 multiplexers added to the conventional fractional‐N frequency divider. © 2002 Wiley Periodicals, Inc. Microwave Opt Technol Lett 33: 355–358, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.10320