Sub-Integer Frequency Synthesis Using Phase-Rotating Frequency Dividers

Abstract

A generalized architecture and theory for realizing multimodulus, sub-integer frequency division is developed by extending the phase-switched divider technique. The sub-integer divider consists of a pre-scaler, a phase rotator, a post-sealer, and a modulus controller. Phase rotation is proposed as an effective technique to realize fine phase resolution and thereby low sub-integer division ratios, as well as to eliminate the glitch which has plagued phase-switched dividers. Program-swallowed counters are used as the modulus controller to realize a broad-range multimodulus divider. Expressions are derived for the range and resolution of such a program-swallowed, phase-rotating divider. Furthermore, the fractional spurs from this divider topology are derived and related to the linearity of the phase rotator. It is shown that very low (-60 to -75 dBc) fractional spurs at the output of the divider can be attained with reasonably accurate phase rotators. The benefit of this technique is in the ability to realize sub-integer frequency synthesizers which have the architectural simplicity of standard integer- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLLs, but the finer frequency resolution capabilities due to sub-integer division.