Spurs are generated at the output of conventional PLLs due to nonidealities of the phase-frequency detector and charge pump, and variation in the modulus of the frequency divider. The former two induces reference spurs while the latter causes fractional spurs. Here, an attempt is made to accurately model the nonidealities and derive the magnitude of spurs. The models presented are based on time-domain analysis of the PLL control voltage which is approximated into rectangular waves for shorter duration and linear waves for longer duration compared to the reference period. The theoretical derivations for reference spurs show a maximum error of 3 dB from the simulated values, while that of fractional spurs show a maximum error of 8 dB. The simulations were performed in 180 nm CMOS technology.