Abstract
In this paper, we propose a 60-GHz fractional- ${N}$ digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( $1/\!f^{3}$ ) and thermal ( $1/\!f^{2}$ ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with $\Sigma \Delta $ dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to $1/\!f^{3}$ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.
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