FPGA SoC Research Articles

π-BA: Bundle Adjustment Hardware Accelerator based on Distribution of 3D-Point Observations

Bundle adjustment (BA) is a fundamental optimization technique used in many crucial applications, including 3D scene reconstruction, robotic localization, camera calibration, autonomous driving, street view map generation, and even space exploration etc. Essentially, BA is a joint non-linear optimization problem, and one which can consume a significant amount of time and power, especially for large optimization problems. Previous approaches of optimizing BA performance heavily rely on parallel processing or distributed computing, which trade higher power consumption for higher performance. In this article we propose $\pi$ π -BA, the first hardware-software co-designed BA hardware accelerator that exploits custom hardware to simultaneously achieve higher performance and power efficiency. Specifically, based on our key observation that not all 3D points appear on all images in a BA problem, we designed a Co-Observation Optimization technique to accelerate BA operations with optimized usage of memory and computation resources. In addition, we developed a hardware-friendly differentiation method, which combines the analytic and forward automatic differentiation to calculate derivatives of projection function in the BA problem. We have implemented the proposed design on an embedded FPGA SoC, and experimental results confirm that $\pi$ π -BA outperforms the existing software implementations in terms of performance and power consumption.

Design and Implementation of FPGA Based Configurable AI Architecture with Deep Learning Algorithm

Our main aim is to design a reconfigurable FPGA architecture using Network on chip using deep learning which act as a validation algorithm. In the Existing System we were using WiNoC (wireless network on chip)which was not reconfigurable. The energy saving in existing model was 55% whereas the proposed model saves upto 83 % of energy. Within the projected system Deep Learning formula is developed in VLSI design with acceptable model is intended on FPGA SOC chip, by that performance are analysed in terms of error rate, regression rate, confusion rate.

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs

AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration; specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx’s IP library.

A Hardware Runtime for Task-Based Programming Models

Task-based programming models such as OpenMP 5.0 and OmpSs are simple to use and powerful enough to exploit task parallelism of applications over multicore, manycore and heterogeneous systems. However, their software-only runtimes introduce relevant overhead when targeting fine-grained tasks, resulting in performance losses. To overcome this drawback, we present a hardware runtime Picos++ that accelerates critical runtime functions such as task dependence analysis, nested task support, and heterogeneous task scheduling. As a proof-of-concept, the Picos++ hardware runtime has been integrated with a compiler infrastructure that supports parallel task-based programming models. A FPGA SoC running Linux OS has been used to implement the hardware accelerated part of Picos++, integrated with a heterogeneous system composed of 4 symmetric multiprocessor (SMP) cores and several hardware functional accelerators (HwAccs) for task execution. Results show significant improvements on energy and performance compared to state-of-the-art parallel software-only runtimes. With Picos++, applications can achieve up to 7.6x speedup and save up to 90 percent of energy, when using 4 threads and up to 4 HwAccs, and even reach a speedup of 16x over the software alternative when using 12 HwAccs and small tasks.

고속 임베디드 기어 검사 시스템을 위한 불량 검출 알고리즘 FPGA 가속화 연구

Gear defects are detected by PC-based machine vision systems for high-speed and high-accuracy inspection. Implementing gear inspection on an embedded platform can enhance power efficiency and lower cost but generally has poorer calculation performance than a PC-based system. Therefore, this paper proposes a power-efficient and high-performance embedded gear inspection system that incorporates accelerated gear inspection algorithms running on an FPGA/ARM SoC software-hardware codesign. First, image processing algorithms for detecting defective gears were proposed. Then, the calculation time for each function was analyzed to find the sources of calculation bottlenecks. The selected heavy load functions such as the minimal enclosing circle function were accelerated by implementing the algorithms to run on FPGA hardware using optimization directives. A prototype of the inspection system was designed to inspect defect gear samples created by a 3D printer. Test results show that through the HW/SW codesign for the FPGA SoC (Xilinx ZCU102), a preprocessing function, such as morphology, and the overall defect inspection process run up to 49 times and 1.98 times faster, respectively, than a software implementation on the same embedded CPU processor.

Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs

A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also creates challenges with respect to security. Architecture for two-factor authentication is designed with low-power, area and with less- human intervention. The proposed model consists of hybrid physical unclonable functions (PUFs) and finite state machine (FSM), which is used to secure the chip and intellectual property (IP) respectively. The PUFs are most often used in recent security applications such as IP protection, IC metering, hardware signature, and obfuscation. This application needs a complex algorithm with a database which consumes more cost and time. In this paper, we have proposed an authentication model consisting of strong and weak PUF with an FSM which can be used for IoT applications. The main focus of this proposal is to authenticate hardware and software IP in circuits. The Experimental evaluation illustrates that the area and power consumed are 5% and 9%, respectively, for authenticating 26 IPs with no false acceptance ratio (FAR) and 1% false rejection ratio (FRR).

OpenCL을 사용한 Intel FPGA SoC 기반 실시간 병렬 다상분해 주파수 대역압축 및 복원 알고리즘

OpenCL을 사용한 Intel FPGA SoC 기반 실시간 병렬 다상분해 주파수 대역압축 및 복원 알고리즘

Development of a readout system for the tentative pixel detectors at HIRFL

This paper presents a common readout system for the development of the pixel detectors at the HIRFL. The readout system consists of the front-end cards (FEC) and the common data acquisition unit (CDAU). The FEC reads data from the customized detector boards and sends it to the CDAU through the high-speed optical fiber link. To reduce the risk of radiation-induced failures, the Flash-based Microsemi Smartfusion2 FPGA SOC has been chosen as the main FPGA on the FEC. The CDAU receives data from the FECs, processes the data and ships the data to the data computer through the PCIe interface. This paper will discuss the design, implementation and first test results of this readout system.

Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications

Dynamic Estimation of Temporary Failure in SoC FPGAs for Heterogeneous Applications

Design and Application Space Exploration of a Domain-Specific Accelerator System

Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

An All-Programmable 16-nm RFSoC for Digital-RF Communications

The Xilinx RFSoC is the first product to integrate cutting-edge RF data converters with an FPGA SoC. This breakthrough integration delivers a dramatic reduction in system power and footprint, while offering increased flexibility for wide-bandwidth communications applications. The RFSoC monolithically integrates a quad-core 1.5-GHz ARM Cortex-A53 application processor, dual-core Cortex-R5 real-time processing units, 4,000 FPGA DSP resources, and up to 16 digital-RF transmit and receive paths. Each RF transmit path includes a 14-bit, 6.4-GS/s RF-DAC and a flexible digital up conversion (DUC) chain. The RF receive channels contain 12-bit, 4-gigasamples per second (GS/s) RF-ADCs and a flexible digital down conversion (DDC) chain. All RF paths include a programmable complex digital mixer with numerically controlled oscillator (NCO), digital compensation of RF paths, on-chip RF-clock generation, and a flexible wideband interface to the FPGA fabric. The device is housed in a 40x40-mm, 1,517-pin ball grid array (BGA) package and is manufactured in a 16-nm Fin field-effect transistor (FinFET) process.

FPGA SoC Based Multichannel Data Acquisition System with Network Control Module

Normally, Data acquisition (DAQ) is used to acquire the signals from different devices like sensors, transducers, actuators etc. The data acquisition is also used to analyze the signals, digitizing the signals and acquiring the signals from different inputs. The main drawbacks in data acquisition system are data storage, hardware size and remote monitoring. The System-on-Chip Field Programmable Gate Array (SoC-FPGA) is used in the proposed system in the aim to reduce the hardware and memory size. Further to provide remote monitoring with Ethernet/Wi-Fi, the Network Control Module (NCM) is integrated with Data acquisition and processing module for the communication between the systems. This developed system achieves high resolution with memory reduction, reduced hardware size, fast remote monitoring and control. It is used for real time processing in DAQ and signal processing. For fault tolerance and portability, the full system reconfigurability based FPGA acts as the best solution and the system can be reused with different configurations. The control of data acquisition and the subsequent management of data are coded in LabVIEW. LabVIEW tool is used to design and develop a four-channel Data Acquisition and Processing (DAQP) unit. National Instruments Data Acquisition (NIDAQ) and National Instruments Field Programmable Gate Array (NIFPGA) are used to test and implement the design for real time processing. This is designed to provide high accuracy, storage and portability.

Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C

High-quality optical flow computation algorithms are computationally intensive. The low computational speed of such algorithms causes difficulties for real-world applications. In this article, we propose an optimized implementation of the classical Combine-Brightness-Gradient (CBG) model on the Xilinx ZYNQ FPGA-SoC, by taking advantage of the inherent algorithmic parallelism and ZYNQ architecture. The execution time decreases to 0.82 second with a lower power consumption (1.881W). It is better than software implementation on PC (Intel i7-3520M, 2.9GHz), which costs 2.635 seconds and 35W. We use C rather than HDLs to describe the algorithm for rapid prototyping.

FPGA‐accelerated deep convolutional neural networks for high throughput and energy efficiency

SummaryRecent breakthroughs in the deep convolutional neural networks (CNNs) have led to great improvements in the accuracy of both vision and auditory systems. Characterized by their deep structures and large numbers of parameters, deep CNNs challenge the computational performance of today. Hardware specialization in the form of field‐programmable gate array offers a promising path towards major leaps in computational performance while achieving high‐energy efficiency.In this paper, we focus on accelerating deep CNNs using the Xilinx Zynq‐zq7045 FPGA SoC. As most of the computational workload can be converted to matrix multiplications, we adopt a matrix multiplier‐based accelerator architecture. Dedicated units are designed to eliminate the conversion overhead. We also design a customized memory system according to the memory access pattern of CNNs. To make the accelerator easily usable by application developers, our accelerator supports Caffe, which is a widely used software framework of deep CNN. Different CNN models can be adopted by our accelerator, with good performance portability. The experimental results show that for a typical application of CNN, image classification, an average throughout of 77.8 GFLOPS is achieved, while the energy efficiency is 4.7× better than an Nvidia K20 GPGPU. © 2016 The Authors. Concurrency and Computation: Practice and Experience Published by John Wiley & Sons Ltd

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks

Communication networks these days face a relentless increase in traffic load. Multi-gigabitper- second links are becoming widespread, and network devices are under continuous stress, so testing whether they guarantee the specified throughput or delay is a must. Software-based solutions, such as packet-train traffic injection, were adequate for lower speeds, but they have become inaccurate in the current scenario. Hardware-based solutions have proved to be very accurate, but usually at the expense of much higher development and acquisition costs. Fortunately, new affordable FPGA SoC devices, as well as high-level synthesis tools, can very efficiently reduce these costs. In this article we show the advantages of hardware-based solutions in terms of accuracy, comparing the results obtained in an FPGA SoC development platform and in NetFPGA-10G to those of software. Results show that a hardware-based solution is significantly better, especially at 10 Gb/s. By leveraging high-level synthesis and open source platforms, prototypes were quickly developed. Noticeable advantages of our proposal are high accuracy, competitive cost with respect to the software counterpart, which runs in high-end off-the-shelf workstations, and the capability to easily evolve to upcoming 40 Gb/s and 100 Gb/s networks.

A single-mode data acquisition architecture for PET/MRI.

The development of MRI compatible detectors based on compact solid state photomultipliers has recently led to simultaneous fully integrated PET/MRI systems for human imaging. The PET acquisition design for MRI integration is known to have several additional constraints, including smaller space, electromagnetic compatibility issues and thermal management. The current work presents the PET acquisition architecture that has been developed for the TRIMAGE project, whose aim is to provide a cost effective, commercial grade trimodality PET/MRI/EEG scanner. The TRIMAGE PET component consists of 216 modules of 2.5 cm x 2.5 cm, arranged in 18 rectangular detectors of 5 cm x 15 cm, the latter in the axial direction, to form a full ring of 31 cm diameter. Each module consists of a staggered dual layer LYSO matrix read out by two arrays of 4 x 8 SiPMs and an ASIC. The detector board hosts a low-power low-end FPGA that performs pixel identification, energy calibration and handles the communication between the ASICs and the motherboard, which is located in proximity of the scanner. Data is streamed using high-density shielded cables and high-speed LVDS transmission to 9 low-end SoC FPGAs and from there to a central mainboard where coincidences and events statistics are processed. Coincidence data is finally transmitted to a host PC for image reconstruction. The proposed architecture and technological solutions will be presented and discussed.

Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described.

A readout system-on-chip for a cubic kilometer submarine neutrino telescope

This contribution reports on the read-out system of the future KM3NeT undersea network of several thousands of synchronized optical detecting nodes. Each node embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and DAQ software designed within the Ice middleware framework resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time stamping of events with nanosecond precision.