Abstract
Gear defects are detected by PC-based machine vision systems for high-speed and high-accuracy inspection. Implementing gear inspection on an embedded platform can enhance power efficiency and lower cost but generally has poorer calculation performance than a PC-based system. Therefore, this paper proposes a power-efficient and high-performance embedded gear inspection system that incorporates accelerated gear inspection algorithms running on an FPGA/ARM SoC software-hardware codesign. First, image processing algorithms for detecting defective gears were proposed. Then, the calculation time for each function was analyzed to find the sources of calculation bottlenecks. The selected heavy load functions such as the minimal enclosing circle function were accelerated by implementing the algorithms to run on FPGA hardware using optimization directives. A prototype of the inspection system was designed to inspect defect gear samples created by a 3D printer. Test results show that through the HW/SW codesign for the FPGA SoC (Xilinx ZCU102), a preprocessing function, such as morphology, and the overall defect inspection process run up to 49 times and 1.98 times faster, respectively, than a software implementation on the same embedded CPU processor.
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