Interconnect Formation Research Articles

Cost effective synthesis of copper oxide nanowires on printed circuit boards

In this paper, an attempt has been made to synthesise copper oxide nanowires on printed circuits. The procedure involves thermal oxidation of substrates in air at a temperature of 450°C. Electron microscope studies confirm the formation of nanowires. X-ray diffraction analysis is done for the samples. A probable mechanism of formation of Cu2O nanowire interconnects is discussed. An analysis of its possible applications is also done.

Interaction of ultra-short laser pulses with CIGS and CZTSe thin films

The thin-film solar cell technologies based on complex quaternary chalcopyrite and kesterite materials are becoming more attractive due to their potential for low production costs and optimal spectral performance. As in all thin-film technologies, high efficiency of small cells might be maintained with the transition to larger areas when small segments are interconnected in series to reduce photocurrent and related ohmic losses in thin films. Interconnect formation is based on the three scribing steps, and the use of a laser is here crucial for performance of the device. We present our simulation and experimental results on the ablation process investigations in complex CuIn1−xGaxSe2 (CIGS) and Cu2ZnSn(S,Se)4 (CZTSe) cell’s films using ultra-short pulsed infrared (~1 μm) lasers which can be applied to the damage-free front-side scribing processes. Two types of processes were investigated—direct laser ablation of ZnO:Al/CIGS films with a variable pulse duration of a femtosecond laser and the laser-induced material removal with a picosecond laser in the ZnO:Al/CZTSe structure. It has been found that the pulse energy and the number of laser pulses have a significantly stronger effect on the ablation quality in ZnO:Al/CIGS thin films rather than the laser pulse duration. For the thin-film scribing applications, it is very important to carefully select the processing parameters and use of ultra-short femtosecond pulses does not have a significant advantage compared to picosecond laser pulses. Investigations with the ZnO:Al/CZTSe thin films showed that process of the absorber layer removal was triggered by a micro-explosive effect induced by high pressure of sublimated material due to a rapid temperature increase at the molybdenum-CZTSe interface.

Connecting Carbon Nanotubes Using Sn

Process of Sn coating on mutiwalled carbon nanotubes (MWCNT) and formation of interconnections among nanotubes are studied using high resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDX). Surface oxidation of nanotubes during heating with HNO3 prior to the SnCl2 treatment and the bonding between functional groups and Sn are found to be responsible for the coating and its stability. Open nanotubes are filled as well as coated during tin chloride treatment. Coating and filling are converted into the coatings on the inner as well as outer walls of the nanotubes during reduction with H2/N2. EDX studies show the formation of intermetallic compounds e.g., Cu6Sn5 and Cu3Sn at the joints between nanotubes. Formation of intermetallic compounds is supposed to be responsible for providing the required strength for bending and twisting of nanotubes joining of nanotubes. Paper presents a detailed mechanism of coating and filling processes, and interconnections among nanotubes.

One‐Dimensional Nano‐Interconnection Formation

Interconnection of one-dimensional nanomaterials such as nanowires and carbon nanotubes with other parts or components is crucial for nanodevices to realize electrical contacts and mechanical fixings. Interconnection has been being gradually paid great attention since it is as significant as nanomaterials properties, and determines nanodevices performance in some cases. This paper provides an overview of recent progress on techniques that are commonly used for one-dimensional interconnection formation. In this review, these techniques could be categorized into two different types: two-step and one-step methods according to their established process. The two-step method is constituted by assembly and pinning processes, while the one-step method is a direct formation process of nano-interconnections. In both methods, the electrodeposition approach is illustrated in detail, and its potential mechanism is emphasized.

A novel flip‐chip interconnection process for integrated circuits

PurposeThe purpose of this paper is to present an outline of the development of a new process for the formation of flip‐chip interconnections using metal coated polymer microparticles.Design/methodology/approachMetal coated polymer microparticles were selectively deposited onto the bondpads of integrated circuits using electrophoresis. Thermocompression bonding was then used to bond the devices to substrates.FindingsParticles obtained a positive surface charge following immersion in an acidic solution and this surface charge allowed the particles to be deposited electrophoretically directly onto the bondpads of an integrated circuit without the need for patterning. Thermocompression bonding of nickel/gold coated particles to gold coated substrates was achieved at temperatures as low as 160°C.Research limitations/implicationsFurther work is needed to test this approach using integrated circuits with finer pitch, and to use patterned substrates for assembly and reliability measurements.Originality/valueThis paper presents a new method for the deposition of metal coated polymer microparticles without the need for any masking or patterning processes for the formation of interconnections on integrated circuits.

A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application

Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.

Hexahapto‐Metal Complexes of Single‐Walled Carbon Nanotubes

AbstractWe report the preparation of organometallic side‐wall complexes of single‐walled carbon nanotubes (SWNTs) under conditions, which allow the study of both mono‐ and bis‐hexahapto SWNT coordination compounds [(η6‐SWNT)Cr(CO)3, (η6‐SWNT)Cr(η6‐C6H6), (η6‐SWNT)2Cr]. The results are interpreted in terms of exohedral and endohedral binding of chromium to the SWNT sidewalls and ligand competition reactions suggest that endohedral binding provides a very stable and kinetically inert mode of organometallic bonding. We demonstrate that the electrical conductivity of SWNT thin films are significantly enhanced by side‐wall bonding to Group 6 transition metals (M = Cr, Mo, and W), which serve to reduce the inter‐carbon nanotube junction electrical resistance by the formation of SWNT interconnects [(η6‐SWNT)2M].

High Density Metal–Metal Interconnect Bonding for 3-D Integration

3-D integration provides a pathway to achieve high performance microsystems through bonding and interconnection of best-of-breed materials and devices. Bonding of device layers can be accomplished by dielectric bonding and/or metal-metal interconnect bonding with a number of metal-metal systems currently under development. RTI has been investigating Cu-Cu and Cu/Sn-Cu interconnect processes for high density area array applications. The interconnect pad fabrication processes and the interconnect bonding conditions (pressure and temperature) required for the formation of low resistance (10's of mΩ), high yielding (≥99.98% bond yield), and reliable interconnects are described. The effects of thermal reliability testing (aging) on electrical connectivity and mechanical strength are presented. Results from the two metal-metal interconnect bonding systems are compared in terms of ease of assembly and small pitch (sub-15 μm ) scaling. Methods for obtaining high bond yield at smaller pitches are discussed.

Matrix metalloproteinase-9 expression in folliculostellate cells of rat anterior pituitary gland

Folliculostellate (FS) cells of the anterior pituitary gland express a variety of regulatory molecules. Using transgenic rats that express green fluorescent protein specifically in FS cells, we recently demonstrated that FS cells in vitro showed marked changes in motility, proliferation, and that formation of cellular interconnections in the presence of laminin, a component of the extracellular matrix, closely resembled those observed in vivo. These findings suggested that FS cells express matrix metalloproteinase-9 (MMP-9), which assists their function on laminin. In the present study, we investigate MMP-9 expression in rat anterior pituitary gland and examine its role in motility and proliferation of FS cells on laminin. Immunohistochemistry, RT-PCR, immunoblotting, and gelatin zymography were performed to assess MMP-9 expression in the anterior pituitary gland and cultured FS cells. Real-time RT-PCR was used to quantify MMP-9 expression in cultured FS cells under different conditions and treatments. MMP-9 expression was inhibited by pharmacological inhibitor or downregulated by siRNA and time-lapse images were acquired. A 5-bromo-2'-deoxyuridine assay was performed to analyze the proliferation of FS cells. Our results showed that MMP-9 was expressed in FS cells, that this expression was upregulated by laminin, and that laminin induced MMP-9 secretion by FS cells. MMP-9 inhibition and downregulation did not impair FS motility; however, it did impair the capacity of FS cells to form interconnections and it significantly inhibited proliferation of FS cells on laminin. We conclude that MMP-9 is necessary in FS cell interconnection and proliferation in the presence of laminin.

2-Substituted imidazole derivatives doped Nafion membrane for high temperature anhydrous application and their performance

One of the technical barriers for high temperature proton exchange membrane fuel cell is the membrane that should have reasonable proton conductivity at reduced relative humidity. In this paper, membranes containing Nafion and 2-substituted imidazole derivatives have been formed through casting process. Imidazole moieties are immobilizied inside the formed membrane though grafting of hydrophobic hydrocarbon chains at 2-position of imidazole. The proton conductivity of the so-formed membranes reaches 6.8×10-3 S cm-1 at 160 °C under anhydrous conditions. Compared to pristine Nafion membrane, the thermal stability of the formed membranes is enhanced. The inter-connected ionic clusters formation has been observed through electrostatic force microscopy. Based on activation energy for proton transportation, the mechanism of proton transportation below and above 120 °C is proposed.

Synthesis of Single Crystalline Tin Nanorods and Their Application as Nanosoldering Materials

Nanosoldering is a promising technique for nanoscale joining and interconnect formation for many newly emerging nanobuilding blocks and nanofabrication processes. In this study, single crystalline tin nanorods are synthesized by a simple, one-pot chemical reduction method assisted by sodium dodecyl sulfate surfactant. The effect of surfactant concentration on the shape variation of tin nanostructures is investigated. The microstructure and the melting behavior of the tin nanorods are characterized. Interconnects of the tin nanorods, either in the form of randomly dispersed networks or dielectrophoretically assembled structures are formed on interdigitated gold electrodes. The I−V electrical properties showed that the contact resistance between nanorods can be significantly lowered by the soldering process. The results show that the tin nanorods are a promising candidate for nanoscale soldering applications.

Engineered Pullulan–Collagen Composite Dermal Hydrogels Improve Early Cutaneous Wound Healing

New strategies for skin regeneration are needed to address the significant medical burden caused by cutaneous wounds and disease. In this study, pullulan-collagen composite hydrogel matrices were fabricated using a salt-induced phase inversion technique, resulting in a structured yet soft scaffold for skin engineering. Salt crystallization induced interconnected pore formation, and modification of collagen concentration permitted regulation of scaffold pore size. Hydrogel architecture recapitulated the reticular distribution of human dermal matrix while maintaining flexible properties essential for skin applications. In vitro, collagen hydrogel scaffolds retained their open porous architecture and viably sustained human fibroblasts and murine mesenchymal stem cells and endothelial cells. In vivo, hydrogel-treated murine excisional wounds demonstrated improved wound closure, which was associated with increased recruitment of stromal cells and formation of vascularized granulation tissue. In conclusion, salt-induced phase inversion techniques can be used to create modifiable pullulan-collagen composite dermal scaffolds that augment early wound healing. These novel biomatrices can potentially serve as a structured delivery template for cells and biomolecules in regenerative skin applications.

Fabrication of high-frequency pMUT arrays on silicon substrates.

A novel technique based on silicon micromachining for fabrication of linear arrays of high-frequency piezoelectric micromachined ultrasound transducers (pMUT) is presented. Piezoelectric elements are formed by deposition of lead zirconia titanate into etched features of a silicon substrate such that the depth of these features determine the element thickness and hence the resonance frequency. The process leaves a near planar surface which is ideal for further wafer level processing such as top electrode and interconnect formation. A fabricated element is characterized by pulse echo response.

Fabrication of high-frequency pMUT arrays on silicon substrates

A novel technique based on silicon micromachining for fabrication of linear arrays of high-frequency piezoelectric micromachined ultrasound transducers (pMUT) is presented. Piezoelectric elements are formed by deposition of lead zirconia titanate into etched features of a silicon substrate such that the depth of these features determine the element thickness and hence the resonance frequency. The process leaves a near planar surface which is ideal for further wafer level processing such as top electrode and interconnect formation. A fabricated element is characterized by pulse echo response.

(Invited) Through-Silicon Via Technology for 3D Applications

The development, characterization, and implementation of electrodeposition processes for IMEC's 3D-WLP flow on 200 mm wafer level is reported. The flow comprises of polymer-isolated Through-Silicon Vias (TSVs), realized on thinned wafers bonded to temporary carriers. Defect-free filling of 25 × 50 μm TSVs with copper was achieved, using IMEC ViaFill chemistry. Copper deposition and a subsequent tin plating in the same process step enables one to create μ-bumps, which then allow for the formation of interconnects between stacked dies. A method is proposed for studying the filling quality by preparing slanted cross-sections by mechanical polishing, which are subsequently inspected using optical microscopy. With this method, one can reveal defects at different levels inside the via and it has the advantage that a large number of TSVs are analysed. In addition to sectioning, an electrical characterization was done on both stacked dies and daisy chains and via chain connectivity is demonstrated.

Ultralow-k / Cu Damascene Multilevel Interconnects Using High Porosity and High Modulus Self-Assembled Porous Silica

We introduced a high porosity ultralow- film into a Cu damascene interconnect without increasing the dielectric constant of a low- film after interconnect formation. A high elastic modulus (9 GPa) with ultralow- value was achieved by using a self-assembled porous silica film formed with UV irradiation and a silylation anneal. Performing the silylation anneal after trench etching results in recovery of the value and dielectric properties. A sidewall protection process carried out before metalization protects the low- film against process-induced damage. The time-dependent-dielectric breakdown lifetime is 10 years at a high electric field of 2.3 MV/cm.

Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration

The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice at 10μm and 15μm pitch in large area arrays are shown. The interconnect bonding process pressure and temperature required for the formation of low resistance (<100 mΩ), high yielding (99.99 % individual bond yield), and reliable interconnects is described. In the case of Cu/Sn-Cu, use of a mechanical key was found to improve yield. A run of 22 consecutive bond pairs was made with the mechanical key, resulting in 98 % aggregate channel yield at 10μm pitch in area arrays containing 325,632 individual bonds per die to achieve an interconnect density of 106 / cm2. SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing are presented. The results of thermal cycling and humidity-temperature testing on electrical yield and resistance are presented for Cu/Sn-Cu with underfill. Comparison of the electrical and shear test performance of Cu/Sn-Cu and Cu-Cu is made. Low temperature bonding (at 210°C, below the melting point of tin) is demonstrated to produce high electrical yield, high shear strength and similar intermetallic compound formation to devices bonded at 300°C. The low temperature process may prove useful for integrating IC devices that have low thermal budgets.

Ink-jetting for Electronic Assembly

We report experimental results on applying ink-jetting to dedicated system-in-package technologies. Special focus is on die-attach, vertical and horizontal interconnects. Our experiments on die attach experiments demonstrate that today we have still too high expenses to adapt materials, filler size and viscosity. The filling experiments of 150μm diameter vertical through encapsulant vias for package-on-package applications with ink-jetting showed void formation, which requires still smaller ink jet drops in the future. For formation of horizontal interconnects, e.g. for rerouting, by ink-jetting we observe that a functionalization of the surfaces e.g. with plasma or sulfur acid is required. Based on these project results and experience we suggest a roadmap for ink-jetting using parallel nozzles and single nozzles.

Low Temperature Electroless Ni–P Catalyst Deposition Enhanced by UV Exposure for Carbon Nanofiber and Nanotube Growth

Electroless Ni–P nanoparticles deposition enhanced by UV exposure was investigated to catalyze the synthesis of carbon nanotubes (CNTs) and carbon nanofibers (CNFs) by thermal chemical vapor deposition at for interconnect formation that can reduce process complexity. The Ni–P nanoparticles with a size of 6–15 nm were deposited by using a UV-assisted electroless plating on the trench wall at for CNF wiring formation. Besides, the Ni–P nanoparticles were selectively deposited at the bottom of the via-hole with a size of 100 nm by using electroless plating at for CNT-via formation.

Formation of Interconnects with Carbon Nanotubes by Nano-Patterning and Acoustics-Assisted Alignment

In this work, the feasibility of self-assembling double-walled carbon nanotubes (DWCNTs) to form nano-sized interconnects over pre-fabricated gold electrodes using a combination of nanopatterning, surface functionalization and acoustics-assisted alignment of the DWCNTs was studied. Self-assembly and concurrent alignment of DWCNTs over the gold electrodes on selectively functionalized surfaces within nano-patterns took place in a fluid medium with the potential scalability for wafer-sized mass production. The adverse impacts of curvature and misalignment of DWCNTs on the chance of their attachment to the target zones were analyzed. Microscopic observations and electrical I-V curve measurements verified that DWCNT interconnects were indeed formed. The results indicated that the fabrication of self-assembled interconnects through the combined usage of nano-patterning, surface functionalization and DWCNT alignment is feasible and is in the right direction towards the fabrication of interconnects for future carbon nanotube-based devices and circuits.