(Invited) Through-Silicon Via Technology for 3D Applications

Abstract

The development, characterization, and implementation of electrodeposition processes for IMEC's 3D-WLP flow on 200 mm wafer level is reported. The flow comprises of polymer-isolated Through-Silicon Vias (TSVs), realized on thinned wafers bonded to temporary carriers. Defect-free filling of 25 × 50 μm TSVs with copper was achieved, using IMEC ViaFill chemistry. Copper deposition and a subsequent tin plating in the same process step enables one to create μ-bumps, which then allow for the formation of interconnects between stacked dies. A method is proposed for studying the filling quality by preparing slanted cross-sections by mechanical polishing, which are subsequently inspected using optical microscopy. With this method, one can reveal defects at different levels inside the via and it has the advantage that a large number of TSVs are analysed. In addition to sectioning, an electrical characterization was done on both stacked dies and daisy chains and via chain connectivity is demonstrated.