Flip Chip Technology Research Articles

Development of flip-chip technology for the optical drive of superconducting circuits

We discuss the flip-chip mounting process of photodiodes and fiber sleeves on silicon substrates to meet the increasing demand for fabrication of highly integrated and hybrid quantum circuits for operation at cryogenic temperatures. To further increase the yield and success rate of the flip-chip procedure, the size of the gold stud bumps, and flip-chip parameters were optimized. Moreover, to connect optical fibers to the photodiodes in an optimal position, the fiber sleeves were aligned with specially fabricated alignment circles before applying thermocompression with the flip-chip machine. The mounted photodiodes were tested at both room temperature and cryogenic temperature, and we find that mechanical imperfections of the sleeve-ferrule combination limit the overall alignment accuracy. The experimental results show that our flip-chip process is very reliable and promising for various optical and electrical applications and, thus, paves the way for fabrication of hybrid chips, multi-chip modules and chip-on-chip solutions, which are operated at cryogenic temperatures.

A Review on CMP Challenges in HWB and Wafer Level Packaging

Chemical mechanical planarization/polishing process faces new challenges in multiple new dimensions as hybrid wafer bonding (HWB) and flip-chip technologies evolve to enable innovative integration forms in semiconductor applications. The advanced capabilities of (i) manufacturing the CMOS independent of the memory array through HWB and, (ii) selecting the fully functional chiplets at the die level for heterogenous components for flip-chip bonding, drive cost-effective and high-performance integration.This paper is a review of the CMP challenges as these new technologies demand additional capabilities such as bonding surface planarization in addition to TSV exposure and polishing ability for backside metallization, edge trimming as well as backside thinning. The toolsets and current capabilities are reviewed in addition to the forthcoming trends of manufacturing ultrathin wafers.

Flip-chip technology at room temperature: A new design of microtube-based interconnect for improved mechanical and electrical properties

Flip-chip assembly of photonic components can be achieved at room temperature by using 10 µm pitch interconnects made of metallised oxide microtubes inserted into ductile reception pads. In order to reduce the electrical resistance of interconnects and the assembly force required, interconnect design in regard to geometry and materials used are optimised through electrical and mechanical finite elements (FEM) simulations. To reduce electrical resistance, one may increase the metallisation thickness or microtube inner diameter. To minimise the assembly force, reducing the reception pad diameter is recommended. Experiments on silicon (Si) test vehicles are conducted to validate these predictions; they indicate that there is no short circuit, with an effectiveness of 100 %. This is achieved first through the assembly of Al-0.5 %wCu metallised oxide microtubes into Al-0.5 %wCu reception pads, using a force less than 10 mN/interconnect and proved to have a resistance of 230 mΩ. Second, with gold (Au) metallised oxide microtubes in indium (In) pads assembled with a force less than 0.7 mN/interconnect. Last interconnects have a resistance of 670 mΩ/interconnect and can still be reduced to 500 mΩ by 2 h annealing at 100 °C.

Development of flip-chip technology for the optical drive of superconducting circuits

We discuss the flip-chip mounting process of photodiodes and fiber sleeves on silicon substrates to meet the increasing demand for fabrication of highly integrated and hybrid quantum circuits for operation at cryogenic temperatures. To further increase the yield and success rate of the flip-chip procedure, the size of the gold stud bumps, and flip-chip parameters were optimized. Moreover, to connect optical fibers to the photodiodes in an optimal position, the fiber sleeves were aligned with specially fabricated alignment circles before applying thermocompression with the flip-chip machine. The mounted photodiodes were tested at both room temperature and cryogenic temperature, and we find that mechanical imperfections of the sleeve-ferrule combination limit the overall alignment accuracy. The experimental results show that our flip-chip process is very reliable and promising for various optical and electrical applications and, thus, paves the way for fabrication of hybrid chips, multi-chip modules and chip-on-chip solutions, which are operated at cryogenic temperatures.

A newly developed Cu(Rh) alloy film and its characteristics and applications

A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere. The new films are next annealed at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 μΩ cm after annealing at 670 °C for 1 h and drifts to 2.26 and 2.14 μΩ after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is then thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670 °C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11 ~ 12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8 nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.Graphical A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere and then annealing the new films at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 mW cm after annealing at 670°C for 1 h and drifts to 2.26 and 2.14 mW after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is next thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670°C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11~12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8-nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.

In situ monitoring of flip chip package process using thermal resistance network method and active thermography

Flip chip technology has been used extensively in microelectronic packaging due to the high density, fine spacing, smaller size. However, the size and spacing of the solder bumps are decreasing gradually, defect detection is getting more and more difficult. Thus, the growing demand for high reliability has generated considerable attention on the importance of defect inspection. This paper proposes an in-situ infrared thermography monitoring method with in situ monitoring system bases on modified thermal resistance network model that added the phase transition for the non-destructive analysis of packaging process. The different defects, such as missing bump and pad, missing bump, and bridge are inspected with an accuracy of up to 90 % based on in situ monitoring system. The maximum error between the model and the experiment is 27.6 %, while the minimum error is 13.6 %. The experiment results show that the max temperature of missing bump and pad, missing bump is 35.43 °C and 6.13 °C higher than normal, and the bridge is 0.44 °C lower than normal, respectively. The maximum amplitude by the Fourier transform is used to inspect due to the max temperature of normal and bridge are indiscernible, the results show that the bridge is 4 lower than normal. The model and experimental results show that the in-situ infrared thermography monitoring method is effective for detecting defects in high density electronic devices. The proposed method of in situ monitoring is expected to provide a new strategy for next generation of three-dimensional heterogeneous integrated chips defect inspection.

Optimizing ultra-wideband balanced power amplifiers through the selection of different output impedance transformation based on SiP techniques

In this paper, two improved ultra-wideband (UWB) balanced power amplifiers based on the flip-chip system-in-package technique and electronic design automation (EDA) are proposed. The conventional approach to system-on-chip (SoC) involves integrating all sub-circuit designs into a single manufacturing process. However, in radio frequency circuits, adopting the SoC approach necessitates intricate matching designs, leading to an increase in development costs. In this study, two types of SiGe unit power amplifiers attempted to achieve a flat S21 response using simpler matching for input/output. The cascode architecture was adopted as the main structure for the first type of unit power amplifier (type I). Subsequently, the design of the second type unit power amplifier was built upon the foundation of the first type, with the only difference being the implementation of two parallel cascode structures (type II), and the primary goal is to enhance both gain and output power compared to the first type. In addition, for this second type unit power amplifier, in conjunction with a quadrature hybrid coupler, the optimal impedance matching value was selected to maintain the flatness of gain across the entire UWB range. Furthermore, the poor performance of S11,22 of these two types of unit power amplifiers was improved by using quadrature hybrid couplers using the WIPD process combined with EDA simulation. Therefore, using flip-chip packaging technology can effectively reduce the increased wafer fabrication costs caused by complex matching designs in active circuits. This improved system has the potential to offer a new practical application for UWB power amplifier design.

InP-based On-board Coherent Tx Front-end with 100-GHz Bandwidth Utilizing Flip-chip Technology Enabling 2-Tb/s/λ Optical Transmission

InP-based On-board Coherent Tx Front-end with 100-GHz Bandwidth Utilizing Flip-chip Technology Enabling 2-Tb/s/λ Optical Transmission

FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch

The impact of the pandemic on the semiconductor and electronics packaging supply chains has been in the news for over a year now. Current projections suggest the supply chain crunch could impact various industries through 2022 and 2023. While there are many ramifications of this shortage, one is certainly the impact on cost. Pricing for packages built with more mature technologies, such as wire bond and flip chip, has changed dramatically. Both of these mature technologies have typically been seen as lower cost options than newer technologies, such as fan-out wafer level packaging (FOWLP). Due to the recent shortages, the cost comparison is no longer as straight-forward as it was before. This paper will analyze the cost of building various packages using flip chip, wire bond, and FOWLP technologies. Factory overhead, indirect costs, and profit margins will be taken into account to turn this into a price comparison, rather than just a comparison of direct costs. The analyses will include the price of a package built using FOWLP technology, the price of flip chip and wire bond packages built before recent supply chain disruptions, and the new expected prices of flip chip and wire bond packages. Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is to understand how supply chain disruptions have changed the cost parity points of wire bond, flip chip, and FOWLP packages.

Defluxing of Copper Pillar Bumped Flip Chips

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and MEMS to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125µm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased. Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 µm and appears to be promising down to pitches of 40µm. Along with reduced pitches, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost. Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product. Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later. The study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch lower than 15 µm and denser packages including 2.5Ds and 3Ds. The cleaning assessment methodologies employed analytical/functional testing including FTIR, Ion Chromatography, SEM/EDX, Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

Optimizing New Power Switch Technology

Power switches are critical components in power conversion for a wide variety of applications, including DC-AC inverters for electric vehicles (EVs), solid state breakers, and energy storage devices. Improving the efficiency and performance of semiconductor power switch components can have wide benefits, improving the efficiency and accelerating deployment of these applications. Compared to conventional power switches, such as insulated-gate bipolar transistors (IGBTs), the B-TRAN™ bidirectional power switch from Ideal Power offers significant improvements in efficiency, reducing power losses by 50% or more depending on the application. With its higher efficiency, B-TRAN results in less heat being generated and thus has significantly lower thermal management requirements. In addition, a single B-TRAN™ replaces multiple conventional power switches for bidirectional applications. Beginning in mid-2020, Ideal Power teamed with QP Technologies, a leading provider of microelectronic packaging and assembly services, to package their B-TRAN switches in various TO packages (a wide range of small-pin-count packages often used for discrete parts such as transistors or diodes). The development work started with TO-247, then moved TO-264 packages, and finally transitioned to a custom direct-bond copper (DBC) solution. To achieve a high-reliability design, QP Technologies and Ideal Power focused on developing die and packaging designs based on flip-chip technology in lieu of wirebonding to maximize the life cycle of the product. This paper investigates the challenges, solutions and finally the fabrication of the first double-sided B-TRAN device.

Effect of flip-chip bonding parameters on the property of passive UHF RFID tags with screen-printed antenna on fabric

The substrate material plays an important role in industrialized flip-chip technology of the passive ultra-high frequency radio frequency identification with antenna printed on flexible film. This work presents the flip-chip fabrication and performance evaluation of ultra-high frequency radio frequency identification with screen-printed antenna on common woven fabrics. The antennas were manufactured by screen printing a stretchable silver-based conductor directly on a common woven nylon fabric. The electrical and mechanical connection between the screen-printed antennas and microchips was formed by flip-chip technology, which bridged the antenna with the microchip under a heating contactor with additive anisotropic conductive adhesives, and the effects of heating contactor parameters (contactor pressure, temperature and duration time) on the performance of radio frequency identification tag prototypes were investigated, and the influence mechanism was discussed in terms of the conductivity, the resonance frequency shift and the morphology. The experiment results show that the flip-chip bonding conditions set in the case of screen-printed antenna on nylon fabric is 0.7 N contactor pressure, 120°C heating temperature and 0.6 s heating duration time, different from the case of previous plastic-like thin film substrate, and this is mainly attributed to the compressive and rough surface of the fabric-based antennas. In addition, the flip-chip heating temperature should be consistent with that of screen-printed conductive ink to ensure a stable electrical connection between the antenna and microchip, as well as good performance of fabric-based ultra-high frequency radio frequency identification tags. These conclusions provide a tool for manufacturing large-scale fabric-based ultra-high frequency radio frequency identification tags and characterizing the process quality.

140-GHz Wideband Array Antenna-in-Package Using Multimode Resonance

A 140-GHz wideband array antenna-in-package (AiP) that uses multimode resonance is proposed based on a low-profile multilayer printed circuit board (PCB), which can be incorporated with flip-chip technology and an integrated transceiver. Using the multiple resonances of a patch and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 monopole-type feeder, a simulated impedance bandwidth of 53% and stable radiation performance over the operating band were achieved. A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> 4 antenna array achieves a gain of up to 18.1 dBi, a radiation efficiency of 80%, and a cross-polarization discrimination (XPD) of over 20 dB. By combining the elements with a feed network composed of striplines, single and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> 4 antenna arrays were designed and fabricated. The capacitance caused by the limitations of the fabrication process was analyzed and overcome using a novel capped-cavity structure. From the experiment, a −10 dB impedance bandwidth of 31% was measured.

Comparative evaluation of the photosynthetic photonic efficiency of white LEDs

White LEDs are an effective solution for light culture due to the presence of the green emission spectrum, which has a positive effect on growing plants in the artificial environment. However, the assessment of the effectiveness of the application of the white LEDs for photoculture is complicated by the lack of information in the technical documentation for LEDs about their photosynthetic photon flux in the range of photosynthetically active radiation. In this regard, the purpose was to measure the photonic and energy characteristics of popular white LEDs in various operating modes and to evaluate their photosynthetic photonic efficiency. High-demand brands of LEDs of the rated power of 0.5W in SMD2835 and SMD3030 housing were selected to be studied. The luminous flux of LEDs was measured using a luminous flux meter using the “integrating sphere” method, and then their luminous efficiency and photosynthetic photonic efficiency were calculated. The highest photosynthetic radiation efficiency (more than 2.7 μmol s−1) was registered for LEDs of the color temperature of 4000K and 5000K in the SMD3030 housing, manufactured using flip-chip technology. LEDs of the color temperature of less than 3000K have the lowest photosynthetic photonic efficiency, which is primarily associated with the energy losses in the phosphor and the presence of radiation in the far-red spectrum region, which is not included in the region of photosynthetically active radiation. White LEDs can be used both separately and in combination with the red and blue LEDs, which will allow selecting the spectral composition of the radiation for the specific species and variety of plants.

Simulation analysis of a specification package for high density and high voltage power module

A novel packaging designing for high density and high voltage power module, namely TPak was proposed. It uses flip-chip welding technology and through-hole technology to avoid the parasitic parameters introduced by wire bonding in traditional electrical interconnection, so that the proposed efficiency of the entire high-voltage module is close to 100%, parasitics are reduced by an order of magnitude, and module manufacturing is simplified and the module mechanical stress capability is improved. The finite element simulation anakysis of heat and force are carried out by means of simulation software, and the problems existing in the current Tpak packaging are analyzed from the perspective of materials, and improvement methods are proposed to optimize performance and improve its reliability.

Cost-Effective Surface-Mount Magnetoelectric Dipole Antenna Based on Ball Grid Array Packaging Technology for 5G Millimeter-Wave New Radio Band Applications

This article presents a cost-effective miniature surface-mount magnetoelectric (ME) dipole antenna. The antenna is realized by a single-layer FR4 substrate and combined with ball grid array (BGA) packaging technology to achieve miniaturization in size. Due to BGA packaging technology, the surface-mount capability allows interconnection between the proposed antenna and other surface-mount devices using a flip-chip interconnect technology, replacing bulky connectors. The proposed antenna element is very compact. Specifically, the electric dipole of the proposed antenna consists of four patches, whereas the magnetic dipole consists of two rows of plated through-holes and a metal ground between them. In addition, the electric and magnetic dipoles are simultaneously excited by an L-shaped metal probe. The prototype has been manufactured and carefully verified. Experimental results show that the proposed antenna element has a −10-dB bandwidth of 23% in the range of 25–31.5 GHz and achieves a peak realized gain of 6.98 dBi at 26 GHz. The dimensions of the proposed antenna element are only 5 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1.8$ </tex-math></inline-formula> mm. The proposed antenna elements can be widely used in the 5G millimeter-wave N257 (26.5–29.5 GHz) and N261 (27.5–28.35 GHz) bands.

Experimental studies on application of silver paste in thermosonic flip-chip bonding

In this subject, thermosonic flip-chip technology was introduced to conduct low-temperature bonding of Ag paste and chip interconnection experiments with micro solder joints. The coating and printing method is used to realize the uniform coating of the Ag paste on the micro Cu pillars, and the thickness of the coated Ag paste can be controlled. During flip-chip bonding, different power, pressure, temperature, and bonding time will affect the shear resistance of the solder joint after bonding. Therefore, this article controls the above factors and only studies the impact of ultrasonic power and pressure on the shear force of the solder joint interface. The experiment found that before reaching the maximum shear force, as the ultrasonic power increases, the shear resistance of the solder joint also gradually increased. After that, as the ultrasonic power increased, the shear resistance of the solder joints gradually decreased. It shows that when using thermosonic flip-chip technology for chip bonding, the ultrasonic power should be maintained in an appropriate range to make the bonded flip-chip solder joints obtain a maximum shear strength. The bonding pressure is proportional to the shear strength of the solder joint.

Welding defect signal extraction technology based on GAMP-SBL algorithm

Flip chip technology has been rapidly developed and widely used in the field of microelectronic packaging, and defect detection has also received more and more attention. Aiming at the problem that noise affects the location and extraction of signal defects in ultrasonic testing, the sparse Bayesian learning based on generalized approximate message passing (GAMP-SBL) algorithm is used to extract signal defects, and the over-complete Gabor dictionary is used to reconstruct signal defects to effectively improve Sparse decomposition algorithm. The precision experiment tested the defect simulation signal and the actual ultrasonic signal respectively, and compared with the greedy algorithm. The experimental results show that the GAMP-SBL algorithm can more effectively extract the defect signal under the noise background.

Intelligent detection technology of flip chip based on H-SVM algorithm

The Flip Chip (FC) technology has been widely used in microelectronic packaging, and the FC technology requires not only higher precision, but also higher reliability, which makes the defect detection of FC more challenging. In this paper, the SAM image of FC is segmented. Histogram of oriented gradient (HOG) as a feature extraction method and optimized support vector machines (SVM) are combined to design an intelligent diagnosis algorithm, which was called H-SVM. This method was used to realize the defect detection of solder bumps. In the same variable environment, it evaluates and compares with other machine learning algorithms. The results show that it is effective to combine HOG and optimized SVM for the diagnosis of convex defects with high detection accuracy.

Research on COB-LED light source with tunable CCT based on screen printing and flip chip technology

Research on COB-LED light source with tunable CCT based on screen printing and flip chip technology