Flicker Noise Research Articles

Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures

The analysis of vertically stacked nanosheet (NS) n-type transistors with two different metal gate-stacks (with a total thickness of 7.5 and 4.7 nm) is presented in this work from room temperature to 200 °C. The focus in this work is on the classical analog figures of merit (FoM). In all NS devices, superior performance is observed that is confirmed by the subthreshold swing variation with temperature, which is very close to the theoretical thermal limit. The Al-based (n*) gate-stack NS n-channel NS field effect transistors (NSFETs) in general present higher transconductance, transistor efficiency, early voltage, and intrinsic voltage gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> ) thanks to the better electrostatic coupling between the gates and the silicon NSs. An A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</sub> of about 47 dB (gate-stack (n*), L = 200 nm, 200 °C) is obtained. The low-frequency noise analysis demonstrates the presence of flicker noise dominated by carrier number fluctuations as the main type of noise and presents a low current noise power spectral density Sid of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-19</sup> A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Hz at a drain current of 1 μA and a drain voltage of 50 mV for a frequency of 10 Hz.

Design Strategies and Architectures for Ultra-Low-Voltage Delta-Sigma ADCs

The design of ultra-low voltage analog CMOS integrated circuits requires ad hoc solutions to counteract the severe limitations introduced by the reduced voltage headroom. A popular approach is represented by inverter-based topologies, which however may suffer from reduced finite DC gain, thus limiting the accuracy and the resolutions of pivotal circuits like analog-to-digital converters. In this work, we discuss the effects of finite DC gain on ultra-low voltage ΔΣ modulators, focusing on the converter gain error. We propose an ultra-low voltage, ultra-low power, inverter-based ΔΣ modulator with reduced finite-DC-gain sensitivity. The modulator employs a two-stage, high DC-gain, switched-capacitor integrator that applies a correlated double sampling technique for offset cancellation and flicker noise reduction; it also makes use of an amplifier that implements a novel common-mode stabilization loop. The modulator was designed with the UMC 0.18 μm CMOS process to operate with a supply voltage of 0.3 V. It was validated by means of electrical simulations using the CadenceTM design environment. The achieved SNDR was 73 dB, with a bandwidth of 640 Hz, and a clock frequency of 164 kHz, consuming only 200.5 nW. It achieves a Schreier Figure of Merit of 168.1 dB. The proposed modulator is also able to work with lower supply voltages down to 0.15 V with the same resolution and a lower power consumption despite of a lower bandwidth. These characteristics make this design very appealing in sensor interfaces powered by energy harvesting sources.

Ultra-Low Noise and Self-Powered β-Ga2O3 Deep Ultraviolet Photodetector Array with Large Linear Dynamic Range

Self-powered ultraviolet (UV) photodetectors are the need of the hour for the current technology to harvest the charge carriers without power consumption. β-Ga2O3 deep UV photodetectors working at zero bias have been investigated here for potential applications in high-definition imaging. The photodetector exhibits an ultralow dark current of 8.6 ± 3.4 fA at zero bias. The initial results of low frequency noise measurements are reported for β-Ga2O3 deep UV photodetectors. An ultralow noise current of 9.1 × 10–16 A/Hz1/2 at 1 Hz is obtained in the self-powered condition. Such an ultralow noise current suggests the potential of this device in detecting very weak optical signals. The thermal noise current limited transport mechanism is found to dominate in comparison to shot noise and flicker noise in the self-powered mode. The linear dynamic range (LDR) of 88.5 dB is achieved which is very useful for high-resolution imaging. The dark current, noise floor, and LDR of the photodetector are the benchmark for β-Ga2O3 self-powered deep UV photodetectors. A 3 × 4 two-dimensional photodetector array with uniform dark and photocurrent across all of the pixels is also demonstrated. The outcomes of the present work are encouraging for imaging applications of β-Ga2O3 based energy-efficient deep UV photodetectors.

A low power low noise analog front-end for ECG recording

This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the proposed amplifier is designed in sub-threshold region which gives high g $$_m$$ /I $$_D$$ ratio. To improve noise efficiency, inverter-based differential input stage is used in this proposed operational transconductance amplifier as it reduces noise by a factor of $$\sqrt{2}$$ when compared to it’s non-inverter based counterpart. In order to decrease flicker noise, large transistors are used in the input stage. Class A–B structure is used in the output stage for achieving high g $$_m$$ /I $$_D$$ ratio and for large output swing range. In 180 nm process the amplifier consumes 477 nW DC power from 1.8 V supply which indicates 7.5% decrease in power consumption when compared to recently reported papers. This amplifier achieves a noise efficiency of 2.68. Common mode rejection ratio and power supply rejection ratio is estimated as 98.5 dB and 104.5 dB respectively.

Analysis and modeling of anomalous flicker noise in long channel halo MOSFETs

Halo implanted MOSFETs exhibit anomalous behavior in drain current power spectral density (SID) of flicker noise (1/f) with the variation in drain voltage, but this behavior cannot be captured by existing 1/f models. To identify the reasons for this abnormal behavior of 1/f noise, we have performed experimentally calibrated technology computer-aided design (TCAD) simulations. We find that this anomalous behavior comes from the drain-side halo region, and it has complex dependence on the bias and geometry. We propose a sub-circuit model for 1/f noise that successfully captures the anomalous behavior of SID with the drain bias. This model calculates the individual contributions and the impact of different device regions, such as the source side halo, channel, and drain side halo, on the overall noise of the device. The proposed model is in good agreement with the experimentally calibrated TCAD simulations for different geometries, biases, and temperatures. The proposed model is also validated with the measurement data.

On Noise Performance of Dual-Gated Silicon FET Biosensors With Schottky Contacts

We analyzed the low-frequency noise (LFN) of dual-gated field-effect transistor (DG-FET) biosensors with Schottky contacts. We found the flicker noise at the sensing insulator-semiconductor interface to be the major noise source while employing Schottky contacts to have minimal noise contribution with a sufficiently large back-gate bias voltage. The measured noise dependence on transconductance further indicated the presence of a nonuniform energy distribution of interface trap density at the said sensing interface. Based on these findings, we argued that the DG structure is advantageous over its single-gated (SG) counterpart; although they possess the same intrinsic lower limit of detection (LLOD), the former could offer a larger signal gain at the optimum LLOD thanks to sufficient channel carrier supply through back-gating instead of biasing the sensing interface toward band edge with higher trap density.

Detailed low frequency noise assessment on GAA NW n-channel FETs

Low frequency noise (LFN) studies are carried out on n-channel gate all around nanowire (GAA NW) FETs. Measurements both as a function of applied polarisation at fixed temperature and conserving the same drain current bias points as a function of temperature are performed, to investigate the predominant flicker noise fluctuation mechanism and to execute low frequency noise spectroscopy allowing to identify the active traps in the depletion area of the devices. The good correlation between the normalized drain current noise SId / Id2 and the transconductance to drain current ratio squared (gm/Id)2 enables to establish that the 1/f noise is related to the carrier number fluctuations mechanisms for all investigated temperatures. The study of the generation recombination (GR) noise as a function of temperature confirms the presence of a GR component for which the characteristic frequency is independent on the applied voltage and present variation with the temperature, suggesting that they are related to active traps located in the Si film. Active traps related to hydrogen and divacancies were identified.

A New True Random Number Generator Based on Differential Variable Ring Oscillator Robust Against PVT Variation

In this paper, a new true random number generator (TRNG) based on a new variable differential ring oscillator has been presented. In this structure, the ring oscillator’s jitter is considered a random phenomenon. The jitter of the proposed ring oscillator is driven by thermal noise and flicker noise so that the generated jitter is random. In this paper, a new variable differential ring oscillator has been designed. The stage of this ring oscillator is changed randomly in order to create random jitter. A new differential delay cell has been proposed to boost the speed of TRNG and random jitter. The proposed random number generator (RNG) is robust against temperature variations of [Formula: see text]40–120[Formula: see text] and voltage variations from 0.8 to 1.8[Formula: see text]V. The proposed system’s bitrate is 50[Formula: see text]MB/s and its efficiency is 30.03[Formula: see text]Mb/mJ. This process has been implemented in the 0.18[Formula: see text]um CMOS process. Simulation results have been presented in Hspice software and cadence. The output bit images have been displayed by Matlab software.

Investigation of Multiple-Mesa-Nanochannel Array GaN-Based MOSHEMTs with Al2O3 Gate Dielectric Layer

In this work, an atomic layer deposition system was used to deposit Al2O3 high-k dielectric film as the gate insulator of GaN-based metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs). By using the Al2O3 gate dielectric layer, compared to planar channel structure, the direct current, high frequency, and flicker noise performances were improved in the GaN-based MOSHEMTs with fin-nanochannel array. For the GaN-based 80-nm-wide fin-nanochannel array MOSHEMTs, they exhibited superior performances of maximum extrinsic transconductance of 239 mS mm−1, threshold voltage of –0.4 V, unit gain cutoff frequency of 7.3 GHz, maximum oscillation frequency of 14.1 GHz, normalized noise power of 2.5 × 10−14 Hz−1, and Hooge’s coefficient of 1.4 × 10−6. The enhanced performances were attributed to the features of fin-nanochannel array of better gate control capability, enhanced pinch-off effect, and better heat dissipation driven by lateral heat flow within the space between fin-channels.

Low-frequency critical current noise in graphene Josephson junctions in the open-circuit gate voltage limit

We investigate critical current noise in short ballistic graphene Josephson junctions in the open-circuit gate-voltage limit within the McWorther model. We find flicker noise in a wide frequency range and discuss the temperature dependence of the noise amplitude as a function of the doping level. At the charge neutrality point we find a singular temperature dependence T^{-3}, strikingly different from the linear dependence expected for short ballistic graphene Josephson junctions under fixed gate voltage.

The Control of Intramolecular Through-Bond and Through-Space Coupling in Single-Molecule Junctions

The Control of Intramolecular Through-Bond and Through-Space Coupling in Single-Molecule Junctions

Design of an Extreme Low Cutoff Frequency Highpass Frontend for CMOS ISFET via Direct Tunneling Principle

In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10-100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

Evaluation of Hot Carrier Impact on Lateral-DMOS with LOCOS feature

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH, ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were found to be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flicker noise assessment under the same stress shows noticeable instabilities.

A 24 GHz Direct Conversion Receiver for FMCW Ranging Radar Based on Low Flicker Noise Mixer

In this paper, a 24 GHz direct conversion receiver (DCR) for frequency-modulated continuous-wave (FMCW) ranging radar based on low flicker noise mixer in 90 nm silicon-on-insulator (SOI) CMOS technology is presented. A low-noise and low-power low-noise-amplifier (LNA) adopting simultaneous noise and input matching (SNIM) method is designed. Neutralized technology and boost inductor are introduced to improve performance. The measurement results of standalone LNA show that the peak gain is 17.2 dB at 23.8 GHz and the −3 dB bandwidth is around 2.2 GHz from 22.8 GHz to 25 GHz. The LNA achieves an average 3 dB NF within the 24 GHz band. A current-bleeding mixer is used to lower noise and the factors influencing flicker noise have been discussed. Proper element values and local oscillator (LO) power have been chosen to make the mixer low-noise. Measurement results illustrate that the receiver exhibits 20.3 dB peak gain, 7 dB SSB noise figure (NF) and −22 dBm IP1dB. Flicker noise of the mixer and the receiver are measured respectively and the noise knee-point of receiver is observed 60 kHz. The receiver consumes only 16 mW with chip area of 0.65 mm2 including pads. The results demonstrate that the proposed receiver can be a promising candidate for FMCW ranging radar.

Process validation test of CNTFET using Stanford model

ABSTRACT Process validation test (PVT) helps to predict the response of a device to various figure of merit (FOM) parameters, such as diameter (process), supply voltage, and temperature. In this paper, the Stanford model is modified to investigate the effect of temperature, nanotube diameter, etc. on the current-voltage characteristics, drain current, transconductance, threshold voltage, subthreshold swing, and conductance of Carbon Nanotube Field Effect Transistors (CNTFETs). To study different parameters in terms of temperature in CNTFETs, we simulate different circuits by adding temperature-dependent voltage/current equations and defining temperature as a parameter in the Stanford model. The results show that an increase in temperature results in higher subthreshold swing, lower on/off current ratio, and lower threshold voltage. Moreover, by adding the variable diameter to the model, we examine its effect on different CNTFET parameters. As diameter increases, both the on/off current ratio and subthreshold swing increase, so the net effect is almost the same. CNTFET noise model is translated in Verilog-A, and then implemented in the ADS simulator. The results show that the shot noise is more noticeable at high frequencies and the flicker noise at low frequencies. Moreover, the noise figure of CNTFET is higher at lower frequencies.

In₂Se₃/Silicon-on-Insulator Heterojunction Phototransistor for Low Noise Dual-Band Detection

In this study, high-performance In2Se3/Silicon-on-Insulator (SOI) heterojunction field-effect transistor photodetector is fabricated. The In2Se3/Si heterostructure phototransistor exhibits dual-band detection with a maximum responsivity of 12 A/W and 41 A/W for illumination of 405 nm and 800 nm wavelengths, respectively. This phototransistor has shown a lower noise-equivalent power of 6.8 fW.Hz $^{-1/2}$ and higher detectivity of $2.9\times 10^{13}$ cm.Hz $^{1/2}\text{W}^{-1}$ . Flicker noise dominates the In2Se3/SOI phototransistor with a corner frequency of 3 Hz. The device’s enhanced performance is due to the improved synergistic effect with efficient electron-hole dissociation in the heterojunction. This heterostructure based photodetector can be of great interest for dual-band (Ultra-violet and visible) detection in imaging, optical communication and healthcare applications.

Use of flicker noise in polyaniline to determine the product of mobility and lifetime of charge carriers

The current passing through a polyaniline layer generates electrical fluctuations, the amplitude of which increases in a part of the frequency spectrum with the inversion of the frequency f. It is deduced that this is due to the behavior of charge carriers trapped on energy levels in the bandgap. If these localized carriers are in equilibrium with the valence band, a frequency range can be found where the lifetime is inversely proportional to the frequency. Electron jumps between the levels and the valence band are manifested by the generation of electrical noise signals. The slope of the dependence of the noise current on 1/f was calculated, and the product of the mobility and lifetime of the holes was determined.

Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation

BSIM-CMG can fit low frequency noise spectrum in the linear region of operation, but deviates in the saturation region of operation, because the noise model used in BSIM-CMG (and also in other MOSFET models) does not include the impact of velocity saturation. In this work, we formulate a unified noise model including the velocity saturation effect and show that the new model accurately captures the experimental data. Additionally, the developed model can be easily implemented in a circuit simulator, with slight modification in the present low frequency noise model. Although this model is developed for BSIM-CMG, it is a generic model and can be used in any industry-standard model like BSIM-BULK, BSIM-IMG, etc. This model is validated with experimental data of 14 nm FinFET technology.

A 101 dB SNR fourth-order ΣΔ modulator for MEMS digital geophones

A fourth-order ΣΔ modulator (SDM) applied for micro-electro-mechanical systems (MEMS) digital geophones is presented in this paper. At the system stage, the proposed fourth-order SDM adopts a hybrid path technology including a feedforward path and a feedback path. At the design stage, a class AB operational transconductance amplifier with a gain bootstrap structure and chopper technique is employed in the first-stage integrator, which can achieve high DC gain, GBW, (Slew Rate) SR and reduce flicker noise, ensuring high (Signal-to-Noise Ratio) SNR for the proposed SDM. Meanwhile, other key modules are designed to meet basic requirements and achieve low power consumption at the same time. The proposed SDM was implemented in the SMIC 0.18 μm CMOS technology and its final area is 3.09 mm2. When the sampling frequency of 512KHz and signal bandwidth of 2KHz are adopted, the measured results show that the proposed fourth-order SDM can achieve SNR of 101 dB and ENOB of 16.4 bits with less than 5mW power consumption, which meet the requirements of high dynamic range and low power in MEMS digital geophones.

Noise and velocity field analysis of crustal movement in Anhui province

Global Navigation Satellite System (GNSS) coordinate time series contains significant information on plate movement and crustal deformation. Through using GAMIT/GLOBK software, we obtained the coordinate time series of Anhui Continuously Operating Reference System (AHCORS) from 2013 to 2018.5. Then power spectral density method and the maximum likelihood estimation method were applied to determine the optimal noise model of AHCORS for the first time. Our results show that the White Noise plus Flicker Noise (WN+FN) model represents the best model for this region. We then solved the linear trend of the obtained coordinate time series using CATS software. Overall, the velocity uncertainty with colored noise is 7 ~ 10 times of that with white noise only, while the average horizontal velocity based on the Eurasian plate is 6.43 mm/a during this period, with a direction of E29.10°S. With respect to the vertical velocity, there is a tendency of subsidence in the north and uplift in the south, with maximum subsidence reaching up to 32.82 mm/a, which appears at station SZDS in Dangshan, Suzhou. The rapid subsidence at this area is most likely due to extraction of groundwater and mineral resources in recent years.