Filter Chip Research Articles

The design of second-order bit sliced infinite impulse response digital filter chips using CIRCAD II : Masuri Othmanet al. Microelectron. J.23, 37 (1992)

The design of second-order bit sliced infinite impulse response digital filter chips using CIRCAD II : Masuri Othmanet al. Microelectron. J.23, 37 (1992)

The design of second-order bit sliced infinite impulse response digital filter chips using CIRCAD II

A digit slicing technique was proposed to speed up the computation of important parameters in digital signal processing. In this paper we describe the use of a technique to produce fast second-order digit sliced IIR digital filter chips. The silicon chip is produced by using an IC design package called CIRCAD II. The digit slicing technique has been described in detail by Z. A. Shariff. The technique involves slicing up either filter coefficients or input data or both into smaller blocks of data with a certain bit width. These smaller blocks, also known as sub-blocks are processed in parallel by the process unit within the sub-blocks, thus speeding up the processing time. A sub-block with a processing unit is also known as a digit convolution module. In our design we sliced both the 16-bit coefficients and the 16-bit input data. Because of the slicing technique, the IC realization of the filter can be done in modular form which thus makes it easy for chip implementation.

A VLSI synthesis tool for complementary output delta modulation FIR filters

An application specific high level synthesis tool is presented for designing linear Delta Modulation (DM) FIR filters, with parallel implementation of their complementary responses, using a Kaiser windowing technique. It is based on a hardware reduction technique which is taking advantage of the special characteristics of DM filters in order to improve their performance concerning noise reduction. The synthesis tool can be linked to various VLSI CAD systems for automated layout construction of high performance DM filter chips. A DM filter chip is demonstrated, compiled by the tool and processed by the VENUS-S semicustom design system.

Design of a high-performance IIR digital filter chip

The design of a novel high-performance IIR digital filter chip is presented. The chip has been implemented using 1.5 μm double-layer metal CMOS technology. The filter chip operates on an 11-bit two's-complement input data, a 12-bit two's-complement coefficient word and produces a two's-complement 14-bit output. The main component of the chip is a fine grained systolic array architecture that internally is based on a signed binary number representation (SBNR). In the paper, the design of the internal array is discussed along with the circuitry necessary to convert data from SBNR to a two's-complement representation. Other important design issues, such as testing and clock distribution, are also addressed.

An 85-MHz fourth-order programmable IIR digital filter chip

The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9- mu m CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10*10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm/sup 2/. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5*10/sup 9/ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency

A digital interpolation filter chip with 32 programmable coefficients designed for baseband pulse shaping in digital microwave radio modems is presented. The chip was designed for a maximum sampling frequency of 80 MHz, under worst-case conditions. The desired throughput rate is achieved by applying a pipelined carry-save arithmetic. Although an optimized pipeline scheme was used, the chip complexity leads to a high capacitive clock load. The synchronization problems and the switching noise problems resulting from this high clock load were solved by dividing the clock system into subsystems and introducing and intended clock skew between the subsystems and by applying a power supply concept in which the global supply lines are consistently routed in a sandwich structure to create an on-chip buffer capacitance. The chip contains 160000 transistors on a silicon area of 78 mm/sup 2/. Typical samples were tested, and although they were fabricated in a moderate 1.5- mu m CMOS technology, their full logical functionality was verified for sampling frequencies of up to 220 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2- mu m CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3*4.3 mm/sup 2/, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New CMOS NIC-based MOSFET-C filters

A new CMOS NIC-based MOSFET-C integrator and its filter applications are presented. Based on this integrator, the required filter chip area and manufacturing cost can be reduced. A third-order elliptic lowpass ladder filter with 0.02dB ripple and bandwidth up to 1.0MHz is designed and simulated. The excellent high frequency performances of these NICs will facilitate the realisation of high frequency integrated filters.

Validation of a VLSI chip using hierarchical colored Petri nets

In this paper we focus on the task of modelling and validating the behavior of a VLSI chip using hierarchical Colored Petri Nets (CP-Nets or CPN's). We discuss current practice in hardware design at the register transfer level. We describe an approach whereby engineering block diagrams, supplemented with suitable formal inscriptions, can be mapped directly to a CPN model. We show in detail a CPN model of an actual digital filter chip from a super-computer. We discuss the possibility of using this model to validate the logic of the design. We describe the potential of using formal analysis methods and propose a simplification technique for reducing the combinatorics involved in Occurrence Graph Analysis. We discuss performance issues and propose an extension to Colored Petri Nets that incorporates the concept of time.

Design of GaAs operational amplifiers for analog sampled data applications

High-grain operational amplifiers for implementation in GaAs technology are an essential component for analog GaAs signal processing systems using switched-capacitor circuit techniques. The requirement for high voltage gains and fast settling times in the context of the inherent technological disadvantages of GaAs (MESFET) devices leads to the development of a whole range of novel circuit techniques. For optimum performance, single-stage designs with single-ended input are considered initially. A description is given of a differential-to-single-ended converter stage that can be combined with these high gain stages to yield differential input amplifiers. A new procedure for characterizing amplifiers in terms of settling time is presented. It reveals the ultimate speed limitation for a given amplifier design and allows the MESFET gatewidths to be scaled in order to obtain optimum settling behavior for any given capacitive load. Ideas are pursued for a new generation of amplifiers with very fast settling times approaching 200 ps, intended for future switched-capacitor systems with 1-GHz switching frequencies. Considerable emphasis is placed throughout on the minimization of chip area and power consumption. The application of one of the amplifier designs in an integrated switched capacitor filter chip is presented, along with encouraging preliminary measurement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Programmable 2D linear filter for video applications

A fully integrated 2-D linear filter including a line buffer for a 7*7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm/sup 2/. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7*7. This chip contains more than 300000 transistors on a silicon area of 103 mm/sup 2/. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design and implementation of a general-purpose median filter unit in CMOS VLSI

A general-purpose median filter unit configuration in the form of two single-chip median filters, one extensible and one real time, is described. The networks of the chips are pipelined and systolic at bit level and based on odd/even transposition sorting. The chips are implemented in 3- mu m standard CMOS using full-custom VLSI design techniques. The exact median of elements, in a window size w=9 with arbitrary word length L, can be found using only one extensible median filter chip. The filter can be extended to arbitrary window size and word lengths by using many chips. Simulation results show that the extensible median filter chip can be clocked up to 40 MHz and can generate 30/L megamedians per second. The real-time median filter chip can find the exact running medians of elements in a window of a fixed size w=9 with L=8. Simulations show that it can generate up to 50 megamedians per second with a 50-MHz clock. The algorithms, VLSI implementations, and chip test results are presented, along with some possible applications. >

A 10.7-MHz switched-capacitor bandpass filter

An experimental 10.7-MHz switched-capacitor bandpass filter is demonstrated that exhibits a 400-kHz bandwidth with a 42-MHz sampling rate. Basic design issues of such high-frequency filters are also addressed with emphasis on dynamic range and power constraints. A theoretical square relation between power and center frequency agrees well with experimental results. The sixth-order differential bandpass filter chip occupies 2 mm/sup 2/ using a 2.25- mu m gate double-poly CMOS technology. >

A fault tolerant oriented CMOS systolic implementation of an FIR filter

The implementation of a FIR digital filter chip based on a systolic array is described. Using the intrinsic regularity of such linear array, the filter can be made fault tolerant with limited additional hardware.

Filter-embedded design and its applications to passive components

A design in which a filter is embedded in a fiber fixed on a substrate is proposed. It was successfully applied to the fabrication of low loss fiber optic components for a single-mode fiber transmission system. These components have a wide operational temperature range. The design is easily adapted to a multifilter or multifiber component. Filter embedding is achieved in two ways. One is to insert a thin filter chip in a slit which is machined into a fiber fixed on a substrate by a dicing saw (filter inserted type). The other is to evaporate a filter film directly on a fiber end face and butt this fiber to another fiber on a guide groove on a substrate (filter evaporated type).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A sliced first-quadrant second-order two-dimensional digital filter chip set for modular filter implementation

Modular Miter structures for two-dimensional (2-D) filters were investigated and a filter function suitable for modular implementation of 2-D digital filters determined. Given this transfer function, a two-chip set was implemented in S micron NMOS technology. This chip set performs an all-pole or all-zero filtering operation in 4-bit slices (i.e. the wordlength is indefinitely expandable in an expansion chain) on a 512 × 512 pixel array using two's complement arithmetic. The chip set may be used as a building block for implementing general first-quadrant 2-D digital filters.

Effects of an adaptive filter hearing aid on speech recognition in noise by hearing-impaired subjects.

In a digitally controlled adaptive filter, ongoing detection and spectral analysis of quasi steady state noise are performed, and analog filter parameters are adjusted to provide greatest attenuation in frequency regions where noise energy is greatest. Attenuation introduced by the filter affects both speech and noise signals in the attenuation region. Effects of a master hearing aid incorporating an adaptive filter chip were assessed by measuring aided speech recognition threshold in noise with and without the filter. Performance of four hearing-impaired subjects showed that filter effects were related both to the frequency spectrum of the noise and to the distribution of speech information by frequency. No improvement in speech recognition threshold was seen for broadband speech materials in broadband noise. Better performance was observed for low-frequency noise in combination with speech materials for which the important information was confined to high frequencies.

Computer Generation of Digital Filter Banks

In order to reduce the design time of digital filter bank circuits, a design system has been developed. The software consists of the filter compiler which converts high level filter descriptions to hardware descriptions and the layout generator which converts the hardware descriptions to a layout file. To verify the algorithms before fabrication, a test system is employed. The development time of this system was kept to a minimum by designing the hardware to be easily micro coded and assembled. Several circuits have been fabricated and tested that were generated with this system, including a single bandpass filter chip, a 112-pole 16-channel filter bank for a speech recognition system and a 16-channel spectrum analyzer for consumer stereo applications. The speech recognition chip achieved a SNR of 80 dB with an area of 25 mm /sup 2/ in a 4-micron NMOS technology.

VLSI implementation of two-dimensional digital filters via two-dimensional filter chips

The realization of an arbitrary two-dimensional (2-D) rational transfer function which represents an infinite impulse response (IIR) 2-D filter in terms of low-order 2-D polynomials is discussed. These low-order polynomials are implemented via a bit-sliced chip, and are used as standard building blocks for the implementation of the general 2-D digital filter. Different general realization methods are considered and are modified in order to incorporate the standard 2-D chips. The resulting structures have reduced complexity and they exhibit a high degree of regularity and modularity. Furthermore, the number of 2-D low-order filter chips required for the implementation of the given filter is substantially reduced, compared to the number of 1-D chips required by regular general implementations.

VLSI implementation of two-dimensional digital filters via two-dimensional filter chips

In this paper we consider the realization of an arbitrary two-dimensional (2-D) rational transfer function, which represents an infinite impulse response (IIR) 2-D filter, in terms of low-order 2-D polynomials. These low-order polynomials are implemented via a bit-sliced chip, and are used as standard building blocks for the implementation of the general 2-D digital filter. Different general realization methods are considered and are modified in order to incorporate the standard 2-D chips. The resulting structures have reduced complexity and they exhibit a high degree of regularity and modularity. Furthermore, the number of 2-D low-order filter chips required for the implementation of the given filter is substantially reduced, compared to the number of 1-D chips required by regular general implementations.