Programmable 2D linear filter for video applications

Abstract

A fully integrated 2-D linear filter including a line buffer for a 7*7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm/sup 2/. The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7*7. This chip contains more than 300000 transistors on a silicon area of 103 mm/sup 2/. In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>