Field Programmable Gate Array Circuit Research Articles

Approximate calculation of 8-point DCT for various scenarios of practical applications

In this paper, based on the parametric model of the matrix of discrete cosine transform (DCT), and using an exhaustive search of the parameters’ space, we seek for the best approximations of 8-point DCT at the given computational complexities by taking into account three different scenarios of practical usage. The possible parameter values are selected in such a way that the resulting transforms are only multiplierless approximations, i.e., only additions and bit-shift operations are required. The considered usage scenarios include such cases where approximation of DCT is used: (i) at the data compression stage, (ii) at the decompression stage, and (iii) both at the compression and decompression stages. The obtained results in effectiveness of generated approximations are compared with results of popular known approximations of 8-point DCT of the same class (i.e., multiplierless approximations). In addition, we perform a series of experiments in lossy compression of natural images using popular JPEG standard. The obtained results are presented and discussed. It should be noted, that in the overwhelming number of cases the generated approximations are better than the known ones, e.g., in asymmetric scenarios even by more than 3 dB starting from entropy of 2 bits per pixel. In the last part of the paper, we investigate the possibility of hardware implementation of generated approximations in Field-Programmable Gate Array (FPGA) circuits. The results in the form of resource and energy consumption are presented and commented. The experiment outcomes confirm the assumption that the considered class of transformations is characterized by low resource utilization.

HARP: Hierarchical Attention Oriented Region-Based Processing for High-Performance Computation in Vision Sensor.

Cameras are widely adopted for high image quality with the rapid advancement of complementary metal-oxide-semiconductor (CMOS) image sensors while offloading vision applications’ computation to the cloud. It raises concern for time-critical applications such as autonomous driving, surveillance, and defense systems since moving pixels from the sensor’s focal plane are expensive. This paper presents a hardware architecture for smart cameras that understands the salient regions from an image frame and then performs high-level inference computation for sensor-level information creation instead of transporting raw pixels. A visual attention-oriented computational strategy helps to filter a significant amount of redundant spatiotemporal data collected at the focal plane. A computationally expensive learning model is then applied to the interesting regions of the image. The hierarchical processing in the pixels’ data path demonstrates a bottom-up architecture with massive parallelism and gives high throughput by exploiting the large bandwidth available at the image source. We prototype the model in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) for integrating with a pixel-parallel image sensor. The experiment results show that our approach achieves significant speedup while in certain conditions exhibits up to 45% more energy efficiency with the attention-oriented processing. Although there is an area overhead for inheriting attention-oriented processing, the achieved performance based on energy consumption, latency, and memory utilization overcomes that limitation.

Implementation and validation of quadral-duty digital PWM to develop a cost-optimized ASIC for BLDC motor drive

In this paper, a quadral-duty digital pulse width modulation (QDPWM) technique-based low-cost hardware architecture for brushless DC (BLDC) motor drive is proposed. The proposed architecture is developed by incorporating an efficient speed calculation and commutation circuitry to achieve the compactness of the total architecture. The speed calculation circuit is designed to perform edge detection of the rotor position signal, with external noise and glitch resistance. The proposed architecture is implemented in the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platform using TSMC 180 nm technology library. The FPGA implementation is compared with existing architectures to validate the resource utilization of the proposed architecture. The ASIC implementation illustrates that the proposed architecture operating at 50 MHz, reduces the gate count and power dissipation to approximately half and one-third, respectively, compared to a standard PI controller based-PWM control architecture. Experimental validation of the FPGA-based architecture is also performed using a laboratory prototype of the BLDC motor drive hardware setup. The performance of the drive is examined for various speed commands and loading conditions. Extensive experimental analysis has been carried out to validate the performance of the proposed architecture-based drive under dynamic load and speed command variation. The ability of the proposed circuit to tolerate the noise in Hall position sensor signals is testified by adding intentional glitches into the signal.

Design Of An Improved And Robust Asynchronous Wrapper (Aw) For FPGA Applications

Contemporary digital systems must be based on the “System-on-Chip – SoC” concept. An interesting style for SoC design is the GALS paradigm (Globally Asynchronous, Locally Synchronous), which can be used to implement circuits in FPGAs (Field Programmable Gate Arrays). However the implementation of asynchronous interfaces (asynchronous wrapper – AW) constitutes a major drawback for this kind of devices. Although there is a typical AW design style, which is based on asynchronous controllers providing communication between modules (called ports), port controllers are subject to essentialhazard when implemented in FPGAs. In this context, this paper proposes a new asynchronous GALS wrapper architecture, suitable for implementations in any kind of FPGAs. The proposed port controllers showed to be essential-hazard-free, not needing any special cares in implementation concerning to LUTs choice. Additional advantages of the proposed architecture are: total autonomy that synchronous modules achieve when interacting with the asynchronous wrapper; the ports can be synthesized in the direct mapping style (so without knowledge of asynchronous logic synthesis); and the ports interact with environment in Ib/Ob Mode, not needing a timing analysis. Simulation results show the applicability of the proposed architecture and lead to its practical implementations in FPGAs.

Field-programmable biological circuits and configurable (bio)logic blocks for distributed biological computing

Synthetic biology applications often require engineered computing structures, which can be programmed to process the information in a given way. However, programming of these structures usually requires significant amount of trial-and-error genetic engineering. This process is to some degree analogous to the design of application-specific integrated circuits (ASIC) in the domain of digital electronic circuits, which often require complex and time-consuming workflows to obtain a desired response.We describe a design of programmable biological circuits that can be configured without additional genetic engineering. Their configuration can be changed in vivo, i.e. during the execution of their biological program, simply with an introduction of programming inputs. These, e.g., increase the degradation rates of selected proteins that store the current configuration of the circuit. Programming can be thus performed in the field as in the case of field-programmable gate array (FPGA) circuits, which present an attractive alternative of ASICs in digital electronics.We describe a basic programmable unit, which we denote configurable (bio)logical block (CBLB) inspired by the architecture of configurable logic blocks (CLBs), basic functional units within the FPGA circuits. The design of a CBLB is based on distributed cellular computing modules, which makes its biological implementation easier to achieve. We establish a computational model of a CBLB and analyse its response with a given set of biologically feasible parameter values. Furthermore, we show that the proposed CBLB design exhibits correct behaviour for a vast range of kinetic parameter values, different population ratios, and as well preserves this response in stochastic simulations.

Power Distribution Attacks in Multitenant FPGAs

The increased use of field-programmable gate arrays (FPGAs) in the cloud and embedded computing environments has led to a number of potential security risks. The sizable amount of logic resources in these devices makes them amenable to sharing across multiple untrusted tenants. However, the co-location of multiple independent circuits presents the possibility of malicious fault injection into an unsuspecting circuit. In this article, the ability of one tenant's FPGA circuit to inject delay faults into another tenant's application located at points across the FPGA die via deliberate supply voltage modulation is investigated. To illustrate the risks involved, a Rivest-Shamir-Adleman (RSA) encryption key extraction attack is performed by introducing delay faults in hardware via voltage manipulations. This attack does not require modification to the encryption core nor require attack activation synchronized with specific encryption operations. Our work characterizes the magnitude of on-chip voltage changes and fault injections over time in relation to the on-chip location of the malicious circuit once an attack is initiated. Strategies to identify power manipulation using low-cost monitoring circuits that can locate the source of an attack are highlighted.

Simultaneous measurement of target distance and azimuth in four quadrant detection

Realize the synchronous solution of target azimuth information and distance information in narrow pulse laser high-speed detection process to improve the time efficiency of detection system. A high-speed analog-to-digital (A/D) sampling chip, field-programmable gate array (FPGA) and related hardware circuit are used to establish a high-speed sampling and signal processing hardware system by performing related program configuration on each chip. Related algorithms such as pulse laser ranging method and azimuth resolution method based on four-quadrant detector are applied. At the same time, the denoising method based on Gauss white noise is adopted. Related simulation experiments and measured experiments are carried out. The simulation and experimental results show that the system realizes the synchronous solution of target azimuth information and distance information during the narrow pulse laser high-speed detection process, in which the distance error is not more than 1% and the azimuth error is not more than 5% and improve resource utilization rate.

FPGA and ASIC realisation of EMD algorithm for real‐time signal processing

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm 2 . For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.

Weakly coupled 10-mode-division multiplexed transmission over 48-km few-mode fibers with real-time coherent MIMO receivers

For weakly coupled mode-division multiplexed (MDM) transmission systems, we design and implement optical coherent receiver prototypes with real-time multiple-input multiple-output (MIMO) digital signal processing to equalize two degenerate linearly polarized modes with dual polarization. Using field programmable gate array circuits, we implement real-value 8 × 2 MIMO adaptive equalization with externally separated phase compensators based on the least mean square algorithm, which enables not only training equalization but also fast carrier-phase tracking. With the optical coherent MIMO receiver prototype, we demonstrate real-time weakly coupled 10 × MDM wavelength-division multiplexed dual-polarization quadrature phase shift keying transmission over 48-km few-mode fibers. This report shows a record number of multiplexed spatial modes, namely, 10 modes with dual polarization, in real-time MDM transmission experiments.

On-Chip System for Fast, High-Range, High-Precision Measurements of Delays

Precision delay measurements are useful for many integrated circuits, especially time-to-digital converters. A new, fully integrated delay measurement circuit using the standard field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC) blocks is presented. This circuit comprises a variable frequency generator built from phase-locked loops, an arbiter, and a control system. The performance of the circuit is evaluated in an FPGA, both as a function of time and over a range of delays. The implementation has demonstrated a delay measurement precision of 2 ps, over a range of 4-14 ns. The circuit incorporates a novel control scheme for continuous calibration of delays, in the presence of variations in the chip due to process, voltage, temperature, or radiation effects. Variations in a single delay setting are measured for 1600 s. The associated power spectral density of the variations reveal 1/f noise below 1 Hz and white noise above at the level of 0.02 ps <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Collections of many delays are measured combined to show that measurement biases in this method are below 2 ps.

Low-complexity parallel real-valued weight adaptive digital combining algorithm for coherent FSO communications employing modes diversity reception under atmospheric turbulence channel

Diversity reception is an effective technology to mitigate the atmospheric turbulence effect on the performance of the coherent free-space optical (FSO) communications. Furthermore, considering high-speed optical communications and the state-of-art clock frequency of state-of-the-art field-programmable gate array (FPGA) or application-specific integrated circuits (ASIC), reducing the computational complexity of digital combining algorithm and analyzing the performance of parallel structure algorithm has become important research issues for diversity reception system. In this paper, we experimentally investigate the performance of a low complexity digital combining algorithm (CA) based on adaptive filter By replacing complex weight with real-valued weight, the number of real multiplications required in digital CA can be reduced by 62.5%. real-valued weight CA also ensuring the similar BER and outage probability performance in terms of serial structure under three different turbulence strengths. For parallel structure algorithm, the performance of real-valued weight CA is superior to that of complex-valued weight CA.

Efficient Method and Architecture for Real-Time Video Defogging

Real-time video defogging has a huge demand in intelligent transportation, advanced driver assistance systems (ADAS), long-range surveillance, autonomous aerial vehicles and endoscopic surgery. Most of these applications are constrained by stringent frame rate, power and memory budget. Till date, the methods devised for such requirements are very rare. Therefore, this paper proposes an efficient method and very-large-scale integration (VLSI) architecture for resource-constrained embedded system targeting real-time video defogging. The method and architecture are co-designed to achieve high throughput while consuming less resources and power. The architecture is divided into four parts namely, atmospheric light estimation unit, airlight adjustment unit, transmission estimation unit, and pixel restoration unit. The atmospheric light estimation unit employs a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times 3$ </tex-math></inline-formula> tile based approach that eliminates the requirement of large buffer memory for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\times 15$ </tex-math></inline-formula> support size. The transmission is estimated using dark channel prior and gradient threshold based Gaussian filtering approach. In order to overcome flickering artifacts, an adaptive airlight updating scheme is employed. From the quantitative and qualitative evaluations, it is observed that the proposed method outperforms the existing hardware approaches. Furthermore, the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations of the architecture achieve a high throughput of 200 MPixels/s and 600 MPixels/s, respectively. The ASIC implementation dissipates 9.03 mW power at 200MHz. Moreover, the proposed design does not require any external memory such as dynamic random-access memory (DRAM), thus making it suitable for on-chip processing that can be closely integrated with an image sensor.

Improved Fuzzy Logic Controller Implemented on FPGA Circuit for Photovoltaic Systems

To be the photovoltaic arrays capable to transport the maximum power obtainable, it must be combined with Maximum Power Point Tracking (MPPT). To succeed, we will improve a Maximum Power Point Tracking (MPPT) method, based on intelligent technique such as Fuzzy Logic Controller (FLC), compared with a conventional method which is P&O. This improved method applied to a stand-alone photovoltaic system under loading conditions and atmospheric data (temperature and irradiance). The goal of this controller is to prove that the FLC is the best technique of MPPT to extract the maximum power of photovoltaic modules. The main objective of this work is the implementation on a “Cyclone II” circuit using “EP2C35F672C6” Development Board reconfigurable Field-Programmable Gate Array (FPGA) with Hardware Description Language (VHDL). Thus, we show the advantages of using the FPGA circuits, which are their short progress time, their low price and their suppleness of process. The close optimum design of this technique is based on the best choice membership functions and control rules for two- input, one-output digital Fuzzy Logic Controller (FLC) based on “Mamdani” mechanism. The simulation and implementation results obtained respectively with waveform under Quartus software and on Cyclone II, both show a satisfactory performance and confirm the good tracking efficacy and speedy response to various atmospheric conditions.

Multi‐core hardware realisation of the quasi maximum likelihood PPS estimator

Multi-core hardware realisation of the quasi maximum likelihood algorithm as the state-of-the-art estimator of polynomial phase signals (PPSs) is proposed in this study. Developed multiple-clock-cycle realisation is suitable for real-time implementation. To prove this, the proposed design is implemented on a field programmable gate array circuit. The hardware realisation is tested and verified on PPSs corrupted with various amounts of the Gaussian noise. Obtained results are compared with software simulations showing excellent match between the proposed system-based and the software-based outputs.

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

FPGA‐based real‐time implementation of a direct torque control with second‐order sliding mode control and input–output feedback linearisation for an induction motor drive

A robust direct torque control (DTC) strategy for an induction motor is proposed in this study. In fact, the proposed control strategy is defined by a combination of DTC, space vector modulation (SVM), input–output feedback linearisation (IOFL), a second-order super-twisting speed controller (STSC), and sliding-mode-load torque and stator-flux observers with stator resistance estimation. First, non-linear IOFL is suggested to achieve decoupled flux and torque control, and the SVM technique is utilised to control the inverter switching frequency which decreases the torque ripples and noise. Second, to improve the speed regulation, an STSC is added to an SVM-DTC-IOFL scheme. Furthermore, the sliding mode observers of the stator flux and of the load torque are proposed in order to improve the control performances by reducing uncertainties and to prevent the effects of the stator resistance variations. Indeed, this study presents the importance of implementing the suggested SVM-DTC-IOFL using a field-programmable gate array (FPGA) circuit. The main interest of the FPGA implementation is the decrease in the control loop delay, due to the parallel processing offered by the FPGA. The performances of the proposed control algorithm are investigated by digital simulation using a Xilinx system generator tool and experimental implementation utilising FPGA-Virtex-5-ML507.

A Backpropagation Neural Network-Based Explicit Model Predictive Control for DC–DC Converters With High Switching Frequency

The explicit model predictive control (MPC) can solve the piecewise control laws offline to save online implementation burden. However, many offline control laws have to be stored to adapt the operating point variation, the correct control law needs to be searched, and the control parameter needs to be calculated. The large storage and computational burdens make the explicit MPC difficult to be applied to the scenarios with high switching and control frequencies. To solve these problems, this article proposes to utilize a backpropagation neural network (BPNN) to fit the input-output relationship of the offline control laws under different operating points. It not only guarantees the control performance but also reduces the storage and computational burden. Such a BPNN method directly calculates the control parameter in a parallel way and thus eliminates serial evaluation of the searching process. Simulation results are provided and compared with the state-of-the-art controls to show the effectiveness of the proposed method. Experimental results demonstrate that a BPNN with 49 parameters can fit more than 10 000 offline control laws, and its implementation can be completed within three clock cycles by field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), so the 1-MHz switching and control frequency can be achieved with 4-MHz clock frequency.

Low-Energy and Fast Spiking Neural Network For Context-Dependent Learning on FPGA

Supervised, unsupervised, and reinforcement learning (RL) mechanisms are known as the most powerful learning paradigms empowering neuromorphic systems. These systems typically take advantage of unsupervised learning because they can learn the distribution of sensory information. However, to perform a task, not only is it important to have sensory information, but also it is required to have information about the context in which the system is operating. In this sense, reinforcement learning is very powerful for interacting with the environment while performing a context-dependent task. The predominant motivation for this brief is to present a digital architecture for a spiking neural network (SNN) model with RL capability suitable for learning a context-dependent task. The proposed architecture is composed of hardware-friendly leaky integrate-and-firing (LIF) neurons and spike timing dependent plasticity (STDP)-based synapses implemented on a field programmable gate array (FPGA). Hardware synthesis and physical implementations show that the resulting circuits can faithfully reproduce the outcome of a learning task previously performed in both animal experimentation and computational modelings. Compared to the state-of-the-art neuromorphic FPGA circuits with context-dependent learning capability, our circuit fires 10.7 times fewer spikes, which accelerates learning 15 times, while requiring 16 times less energy. This is a significant step in achieving fast and low-energy SNNs with context-dependent learning ability on FPGAs.

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits

Nanotechnology is an important technological alternative to overcome the limitations of complementary metal-oxide-semiconductor (CMOS) technology. Various circuit implementation methods based on nanotechnology have been proposed, and their most important characteristics are a high defect ratio and defect tolerance through circuit reconfiguration. CMOS-nanowire-MOLecular (CMOL) field-programmable gate array (FPGA) circuits are advanced logic circuit structures that combine the advantages of CMOS and nanotechnology. However, researches on defect diagnosis methods for the reconfiguration of CMOL FPGA circuits are barely conducted. In this paper, efficient circuit configuration methods for defect diagnosis of the CMOL FPGA circuits are proposed to address the problem. Also, diagnosis algorithms for both stuck-at open and stuck-at close defects are introduced. Experimental results show that with the proposed methods, diagnosis is possible for CMOL fabrics with up to 20% stuck-at open defects and 0.02% or more stuck-at close defects.

Real-Time Event Handling and Preemptive Hardware RTOS Scheduling on a Custom CPU Implementation

The rapid evolution of field-programmable gate array (FPGA) devices has strongly influenced both the design methodology and development tools. This article describes an original implementation based on a hardware structure used for static and dynamic task scheduling. The proposed custom processor has hardware-implemented RTOS (HW-RTOS) features and is verified using an FPGA circuit. The solution replaces the classical stack save concept with a resource remapping mechanism that enables a new task to be executed starting with the next processor cycle. The proposed hardware scheduler enables unified management of events and interrupts, by implementing a method of attaching interrupts to tasks while ensuring the requirements of real-time systems. The robustness and performance of the proposed platform are guaranteed by the context switch operations, presence of the intertask synchronization and communication mechanisms, and by the efficient use of the multiplexed resources. Instead of saving and restoring general-purpose registers into the memory, the latency is removed by directly commuting the datapath task resources.