Implementation and validation of quadral-duty digital PWM to develop a cost-optimized ASIC for BLDC motor drive

Abstract

In this paper, a quadral-duty digital pulse width modulation (QDPWM) technique-based low-cost hardware architecture for brushless DC (BLDC) motor drive is proposed. The proposed architecture is developed by incorporating an efficient speed calculation and commutation circuitry to achieve the compactness of the total architecture. The speed calculation circuit is designed to perform edge detection of the rotor position signal, with external noise and glitch resistance. The proposed architecture is implemented in the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) platform using TSMC 180 nm technology library. The FPGA implementation is compared with existing architectures to validate the resource utilization of the proposed architecture. The ASIC implementation illustrates that the proposed architecture operating at 50 MHz, reduces the gate count and power dissipation to approximately half and one-third, respectively, compared to a standard PI controller based-PWM control architecture. Experimental validation of the FPGA-based architecture is also performed using a laboratory prototype of the BLDC motor drive hardware setup. The performance of the drive is examined for various speed commands and loading conditions. Extensive experimental analysis has been carried out to validate the performance of the proposed architecture-based drive under dynamic load and speed command variation. The ability of the proposed circuit to tolerate the noise in Hall position sensor signals is testified by adding intentional glitches into the signal.