FPGA and ASIC realisation of EMD algorithm for real‐time signal processing

Abstract

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead of using separate modules for each calculation. In this work, the traditional cubic spline interpolation has been replaced with sawtooth transform followed by a smoothing module called moving average. In this study firstly, Verilog-HDL code for the EMD is written using Xilinx Vivado and tested in the simulation phase, later dumped into Digilentinc Basys 3 FPGA board to do the hardware verification. For ASIC, the code is synthesised using Cadence Genus tool with the semi-conductor laboratory 180 nm cell library and the layout is made in the Cadence Innovus tool. The proposed EMD can work with a clock/sampling rate up to 25 MHz and has a layout area of 3.9 mm 2 . For the reduction of power consumption of the overall system, clock gating has been used which helps to reduce the dynamic power of the modules, when they are not in use.