Field Programmable Analog Array Research Articles

Applications of Current-Starved Inverters to Music Synthesis on Field Programmable Analog Arrays

Applications of Current-Starved Inverters to Music Synthesis on Field Programmable Analog Arrays

MEMS Seismic Sensor with FPAA-Based Interface Circuit for Frequency-Drift Compensation Using ANN

Abstract Electrochemical micro-electro mechanical systems (MEMS) seismic sensor is limited by its nonideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware. These digital circuits are limited by inherent analog to digital conversions which consumes significant power, acquires more size and limits processing speed. This system presents field programmable analog array (FPAA) (Anadigm AN231E04) based hardware implementation of artificial neural network (ANN) model with minimized error in frequency drift in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99%. Single neuron consumes power of 206.62 mW with minimum block wise resource utilization. The proposed hardware uses all analog blocks removing the requirement of analog to digital converter and digital to analog converter, reducing significant power and size of interface circuit and enhancing processing speed. It gives the reliable, SMART MEMS seismic sensor with ANN-based intelligent interface circuit implemented in FPAA hardware.

Constructing Infinitely Many Attractors in a Programmable Chaotic Circuit

In this paper, we modify the Sprott M chaotic system to provide infinitely many co-existing attractors by replacing the offset boosting parameter with a periodic function giving what we call a self-reproducing system. Consequently, a chaotic signal with either polarity can be obtained by selecting different initial conditions. Various periodic functions are introduced in the same offset-boostable system for producing coexisting attractors. We used a field programmable analog array to construct a programmable chaotic circuit, and the predicted attractors were observed on an oscilloscope.

Versatile Locomotion Control of a Hexapod Robot Using a Hierarchical Network of Nonlinear Oscillator Circuits

A novel hierarchical network based on coupled nonlinear oscillators is proposed for motor pattern generation in hexapod robots. Its architecture consists of a central pattern generator (CPG), producing the global leg coordination pattern, coupled with six local pattern generators, each devoted to generating the trajectory of one leg. Every node comprises a simple nonlinear oscillator and is well-suited for implementation in a standard field-programmable analog array device. The network enables versatile locomotion control based on five high-level parameters which determine the inter-oscillator coupling pattern via simple rules. The controller was realized on dedicated hardware, deployed to control an ant-like hexapod robot, and multi-sensory telemetry was performed. As a function of a single parameter, it was able to stably reproduce the canonical gaits observed in six-legged insects, namely the wave, tetrapod, and tripod gaits. A second parameter enabled driving the robot in ant-like and cockroach-like postures. Three further parameters enabled inhibiting and resuming walking, steering, and producing uncoordinated movement. Emergent phenomena were observed in the form of a multitude of intermediate gaits and of hysteresis and metastability close to a point of gait transition. The primary contributions of this paper reside in the hierarchical controller architecture and associated approach for collapsing a large set of low-level parameters, stemming from the complex hexapod kinematics, into only five high-level parameters. Such parameters can be changed dynamically, an aspect of broad practical relevance opening new avenues for driving hexapod robots via afferent signals from other circuits representing higher brain areas, or by means of suitable brain-computer interfaces. An additional contribution is the detailed characterization via telemetry of the physical robot, involving the definition of parameters which may aid future comparison with other controllers. The present results renew interest into analog CPG architectures and reinforce the generality of the connectionist approach.

Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits

Synthesis and design methodology suitable for computer-aided design tools are now emerging as major challenge for analog system designers. This paper proposes a systematic synthesis procedure which provides reusability and programmability, for linear and nonlinear analog circuits using configurable building block (CBB) and analog cell (AC). Operational transconductance amplifier-based ACs are synthesized in terms of CBBs. Reusability and programmability of the synthesis methodology have been demonstrated by realizing different types of linear and nonlinear circuits and mapping those circuits in field programmable analog array. Finally, the proposed methodology has been integrated as an electronic design automation tool AnaSyn1.0. Performance of all the proposed circuits has been verified by SPICE simulation.

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of $$-\,2$$ . Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/− 1 LSB and the INL is + 1.8/− 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is $$1.6\,\upmu$$ A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of $$400 \times 500\,{\mathrm{mm}}^2$$ .

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays * * Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.

Linear synchronization and circuit implementation of chaotic system with complete amplitude control * *Project supported by the Startup Foundation for Introducing Talent of Nanjing University of Information Science & Technology, China (Grant No. 2016205), the Natural Science Foundation of the Jiangsu Higher Education Institutions of Jiangsu Province, China (Grant No. 16KJB120004), the Priority Academic Program Development of Jiangsu Higher Education

Although chaotic signals are considered to have great potential applications in radar and communication engineering, their broadband spectrum makes it difficult to design an applicable amplifier or an attenuator for amplitude conditioning. Moreover, the transformation between a unipolar signal and a bipolar signal is often required. In this paper, a more intelligent hardware implementation based on field programmable analog array (FPAA) is constructed for chaotic systems with complete amplitude control. Firstly, two chaotic systems with complete amplitude control are introduced, one of which has the property of offset boosting with total amplitude control, while the other has offset boosting and a parameter for partial control. Both cases can achieve complete amplitude control including amplitude rescaling and offset boosting. Secondly, linear synchronization is established based on the special structure of chaotic system. Finally, experimental circuits are constructed on an FPAA where the predicted amplitude control is realized through only two independent configurable analog module (CAM) gain values.

Calibration of Floating-Gate SoC FPAA System

We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform

This paper investigates the variability of various circuits and systems over temperature and presents several methods to improve their performance over temperature. The work demonstrates use of large scale reconfigurable System-On-Chip (SOC) for reducing the variability of circuits and systems compiled on a Floating Gate (FG) based Field Programmable Analog Array (FPAA). Temperature dependencies of circuits are modeled using an open-source simulator built in the Scilab/XCOS environment and the results are compared with measurement data obtained from the FPAA. This comparison gives further insight into the temperature dependence of various circuits and signal processing systems and allows us to compensate as well as predict their behavior. Also, the work presents several different current and voltage references that could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment that could be easily compiled on the FPAA. An FG based current reference is then used for biasing a 12 × 1 Vector Matrix Multiplication (VMM) circuit and a second order G m − C bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large scale FG FPAA presented here is fabricated in a 350 nm CMOS process.

Field-programmable analogue arrays for the sensorless control of DC motors

ABSTRACTThis work presents the analogue implementation of a sensorless controller for direct current motors based on the super-twisting (ST) sliding mode technique, by means of field programmable analogue arrays (FPAA). The novelty of this work is twofold, first is the use of the ST algorithm in a sensorless scheme for DC motors, and the implementation method of this type of sliding mode controllers in FPAAs. The ST algorithm reduces the chattering problem produced with the deliberate use of the sign function in classical sliding mode approaches. On the other hand, the advantages of the implementation method over a digital one are that the controller is not digitally approximated, the controller gains are not fine tuned and the implementation does not require the use of analogue-to-digital and digital-to-analogue converter circuits. In addition to this, the FPAA is a reconfigurable, lower cost and power consumption technology. Simulation and experimentation results were registered, where a more accurate transient response and lower power consumption were obtained by the proposed implementation method when compared to a digital implementation. Also, a more accurate performance by the DC motor is obtained with proposed sensorless ST technique when compared with a classical sliding mode approach.

New alternatives for analog implementation of fractional-order integrators, differentiators and PID controllers based on integer-order integrators

In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulation of a rational function in a similar way to the reported for the synthesis of the variable-state filters. The advantage of the proposed implementation is the requirement of only simple analog design blocks, such as integrators (of integer order), differential amplifiers and two-input adder amplifiers. Most important, contrarily to other reported solutions, the proposed realization can be fulfilled using commercially available resistors and capacitors, with a reduced number of calculations, and without negative impedance converters or inductors. In addition, the orders of the fractional derivative and integral can be modified just varying the gain of the differential amplifiers and adders. To validate the proposal of implementation, and as example of application, we present simulations (HSPICE, MATLAB) and experimental results of a first-order plus dead time plant controlled by fractional-order PI and PID controllers. The experimental results were obtained from a realization using field-programmable analog arrays. A comparison analysis highlights that the proposed alternative of implementation presents advantages regarding a Cauer-network-based realization in terms of number of active and passive elements, number of passive elements with non-commercial available values and design complexity.

Single-Objective Path Planning for Autonomous Robots Using Reconfigurable Analog VLSI

This paper presents path planning using reconfigurable analog very large scale integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application specific integrated circuits (ASICs) can theoretically be used for path planning. There are two main drawbacks to using custom ASICs: 1) circuit designs are fixed to some extent (not changeable) and 2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called field-programmable analog arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents an algorithm for mapping a robot’s environment onto an FPAA, and then presents hardware results using an FPAA to implement the path-planning algorithm. Experimental results and analysis are presented for 24 environment scenarios. Digital search methods like breadth-first search have solutions which scale on the order of $\boldsymbol {O( {4^{d}} )}$ whereas this paper will show our analog solution is on the order of $\boldsymbol {O( d )}$ where ${d}$ is the depth of the solution.

Tuning of Multiple Parameters With a BIST System

This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for local mismatch and variations in the bias current, and mismatch in parasitic and routing capacitances. The bandpass filters are biased in subthreshold regime and the system of 12 parallel filter banks consumes a power of $7.072~\mu \text{W}$ . The proposed tuning algorithm reduces variation in center frequency to 5.07% compared with a variation of 10.16% when they are not tuned, variation in quality factor to 8.52% from 13.86%, and variation in the gain at the center frequency to 3.83% from 21.04%. These values are deviation of the parameters from its mean for the data taken from three different FPAA chips fabricated on the same wafer.

FPAA-Based Control of Bilateral Teleoperation Systems for Enhanced User Task Performance

In a bilateral teleoperation system, discrete-time implementation of the controller can cause performance degradation. This is due to a well-known stability-imposed upper bound on the product of the discrete-time controller's gain and the sampling period. In this article, for a bilateral teleoperation system, a continuous-time controller based on a Field Programmable Analog Array (FPAA) is deployed and compared in terms of performance with its discrete-time counterpart. Experimental results show that, unlike the discrete-time controller, the FPAA-based controller helps the human user complete teleoperation tasks that require high controller gains such as when a large impedance needs to be displayed against the user's hand. Also, an experimental object stiffness discrimination study shows that large sampling periods, necessitating low control gains for maintaining stability, lead to unacceptable task performance by the user; however, the users show an improved ability to discriminate the various objects if the teleoperation controller is implemented using an FPAA.

Modeling, simulation and implementation of circuit elements in an open-source tool set on the FPAA

An open-source simulator to design and implement circuits and systems, replicating the results from the Field Programmable Analog Array (FPAA) is presented here. The fundamental components like the transistors, amplifiers and floating gate devices have been modeled based on the EKV model with minimal parameters. Systems including continuous-time filters and the analog front-end of a speech processing system have been built from these basic components and the simulation results and the data from the FPAA are shown. The simulated results are in close agreement to the experimental measurements obtained from the same circuits compiled on the FPAA fabricated in a 350 nm process.

HDL-Based Synthesis System with Debugger for Current-Mode FPAA

The study demonstrates original environment for synthesizing and implementing current-mode analog circuits in the field programmable analog array (FPAA) technology. The described approach is inspired by existing solutions for digital circuits, implemented using a field programmable gate array. The tools are compatible with the existing hardware architecture description standards (VHDL-AMS, HSPICE) and the existing electronic design automation software. The functionality of the system was divided into a synthesis stage (independent on the hardware layer) and an implementation stage (dedicated to an FPAA platform chosen by the user). This article presents parasitics oriented place&route algorithms of the original system and a method for calibrating the analog part. The tools are also equipped with the option of debugging a programmed circuit. The author presents the functionality of the system with an example of an implementation of a 5th order filter pair and a 35–18–26 perceptron with a balanced structure. The summary is an analysis of the complexity of the implemented algorithms and the measurement of program run-times.

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital–analog converter, an elliptic filter with SNR,=,40.42 dB, 2D-DCT processor with PSNR,=,53.05 dB and RGB-to-YCrCb converter with PSNR,=,46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

Design of a high‐bandwidth tripod scanner for high speed atomic force microscopy

Tip-scanning high-speed atomic force microscopes (HS-AFMs) have several advantages over their sample-scanning counterparts. Firstly, they can be used on samples of almost arbitrary size since the high imaging bandwidth of the system is immune to the added mass of the sample and its holder. Depending on their layouts, they also enable the use of several tip-scanning HS-AFMs in combination. However, the need for tracking the cantilever with the readout laser makes designing tip-scanning HS-AFMs difficult. This often results in a reduced resonance frequency of the HS-AFM scanner, or a complex and large set of precision flexures. Here, we present a compact, simple HS-AFM designed for integrating the self-sensing cantilever into the tip-scanning configuration, so that the difficulty of tracking small cantilever by laser beam is avoided. The position of cantilever is placed to the end of whole structure, hence making the optical viewing of the cantilever possible. As the core component of proposed system, a high bandwidth tripod scanner is designed, with a scan size of 5.8 µm × 5.8 µm and a vertical travel range of 5.9 µm. The hysteresis of the piezoactuators in X- and Y-axes are linearized using input shaping technique. To reduce in-plane crosstalk and vibration-related dynamics, we implement both filters and compensators on a field programmable analog array. Based on these, images with 512 × 256 pixels are successfully obtained at scan rates up to 1024 lines/s, corresponding to a 4 mm/stip velocity. SCANNING 38:889-900, 2016. © 2016 Wiley Periodicals, Inc.

Reconfigurable analog classifier for knee-joint rehabilitation.

We present a System-On-Chip Field Programmable Analog Array (FPAA) for analyzing and processing the signals off an accelerometer for a wearable joint health assessment device. FPAAs have been shown to compute with an efficiency of 1000 times, as well as area efficiencies of 100 times, more than digital solutions. This work presents a low power signal processing system which allows us to extract features from the output of the accelerometer. These features are used by the classifier, implemented using a vector matrix multiplication and a two output 1-winner-take-all, to detect flexion and extension cycles in the subject. The compiled design consumes 0.636 μW of power for the front end analog signal processing chain where as the single layer classifier uses 13 μW of power. Thus the system is highly suitable for wearable applications where power consumption is a major concern. The current FPAA is fabricated in a 0.35 μm CMOS process and is operated at a power supply of 2.5 volts. The Gm-C filters and other circuits are operated in the subthreshold regime of the transistor to obtain the highest transconductance to current ratio offered by the process.