Field Effect Diode Research Articles

Achieving ultralow leakage current in Schottky-MIS cascode anode lateral field-effect diode based on AlGaN/GaN HEMT

In this paper, we design and fabricate a Schottky-metal-insulator-semiconductor (MIS) cascode anode GaN lateral field-effect diode (CA-LFED) to achieve ultralow reverse leakage current (ILEAK). The device based on AlGaN/GaN high-electron-mobility-transistor (HEMT) includes a normally-off MIS-controlled channel that is cascoded with a high barrier height Schottky contact. At reverse bias, the high electric-field is effectively prevented by the normally-off MIS-controlled channel edge. Together with the high barrier height Schottky contact, this feature significantly suppresses the ILEAK. Supported by the device fabrication, the CA-LFED with high breakdown voltage (BV) > 600 V shows an ultralow ILEAK of 3.6 × 10−9 A/mm as well as a low forward voltage drop (VF) of 2.2 V. The performance suggests that the CA-LFED can be a promising candidate for ultralow ILEAK and better VF-ILEAK trade-off GaN power diode applications.

Low-Voltage IGZO Field-Effect Ultraviolet Photodiode

Abstract In the era of Internet of Things (IoTs), an energy-efficient ultraviolet (UV) photodetector (PD) is highly desirable considering the massive usage scenarios such as environmental sterilization, fire alarm and corona discharge monitoring. So far, common self-powered UV PDs are mainly based on metal-semiconductor hetero-structures or p–n heterojunctions, where the limited intrinsic built-in electric field restricts further enhancement of the photoresponsivity. In this work, an extremely low-voltage field-effect UV PD is proposed using a gate-drain shorted amorphous IGZO (a-IGZO) thin film transistor (TFT) architecture. A combined investigation of the experimental measurements and technology computer-aided design (TCAD) simulations suggests that the reverse current (I R) of field-effect diode (FED) is highly related with the threshold voltage (V th) of the parental TFT, implying an enhancement-mode TFT is preferable to fabricate the field-effect UV PD with low dark current. Driven by a low bias of −0.1 V, decent UV response has been realized including large UV/visible (R 300/R 550) rejection ratio (1.9 × 103), low dark current (1.15 × 10−12 A) as well as high photo-to-dark current ratio (PDCR, ∼ 103) and responsivity (1.89 A/W). This field-effect photodiode provides a new platform to construct UV PDs with well-balanced photoresponse performance at a low bias, which is attractive for designs of large-scale smart sensor networks with high energy efficiency.

Low power nanoscale S-FED based single ended sense amplifier applied in integrate and fire neuron circuit

Current advancements in neuromorphic computing systems are focused on decreasing power consumption and enriching computational functions. Correspondingly, state-of-the-art system-on-chip developers are encouraged to design nanoscale devices with minimum power dissipation and high-speed operation. This paper deals with designing a sense amplifier based on side-contacted field-effect diodes to reduce the power-delay product (PDP) and the noise susceptibility, as critical factors in neuron circuits. Our findings reveal that both static and dynamic power consumption of the S-FED-based sense amplifier, equal to 1.86 μW and 1.92 fW/GHz, are × 243.03 and × 332.83 lower than those of the conventional CMOS counterpart, respectively. While the sense-amplifier circuit based on CMOS technology undergoes an output voltage deviation of 170.97 mV, the proposed S-FED-based one enjoys a minor output deviation of 27.31 mV. Meanwhile, the superior HIGH-level and LOW-level noise margins of the S-FED-based sense amplifier to the CMOS counterparts (∆NMH = 70 mV and ∆NML = 120 mV), respectively, can ensure the system-level operation stability of the former one. Subsequent to the attainment of an area-efficient, low-power, and high-speed S-FED-based sense amplifier (PDP = 187.75 × 10–18 W s) as a fundamental building block, devising an innovative integrate-and-fire neuron circuit based on S-FED paves the way to realize a new generation of neuromorphic architectures. To shed light on this context, an S-FED-based integrate-and-fire neuron circuit is designed and analyzed utilizing a sense amplifier and feedback loop to enhance spiking voltage and subsequent noise immunity in addition to an about fourfold increase in firing frequency compared to CMOS-based ones.

Superior energy-delay-production in nanoscale field effect diode by embedded doped pockets for digital applications

Superior energy-delay-production in nanoscale field effect diode by embedded doped pockets for digital applications

A performance evaluation of a novel field-effect device as an alternative to the field-effect diode

A performance evaluation of a novel field-effect device as an alternative to the field-effect diode

Single event performance of FED based SRAMs using numerical simulation

In this work, single event performance of field effect diode (FED) devices have been investigated. Three variations of FED structures have been taken up for the study, and they are, (i) regular FED, (ii) modified FED-I, and (iii) modified FED-II. The study can be split into parts, (i) single event transients (SET) in the FED devices which is used to extract the sensitive location of the device, and (ii) single event upsets in FED-based SRAM cells which is used to extract the critical radiation dose i.e. the minimum dose required to flip the cell content. Among the three FED structures, the collected charge due to SET is maximum in regular FED structure, and the critical dose is minimum in regular FED structure. From the MOSFET literature, it has been found that the single event performances of the MOSFET devices are much superior to the FED devices.

Role of Phonon Scattering in a Junctionless Carbon Nanotube Field-Effect Diode

Role of Phonon Scattering in a Junctionless Carbon Nanotube Field-Effect Diode

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

Suppression of injected minority carriers in nanoscale field effect diodes to improve the off-current

Suppression of injected minority carriers in nanoscale field effect diodes to improve the off-current

Bulk Field Effect Diode

The field effect diode (FED) is an attractive device to use in various digital and analog applications, but all previously proposed FEDs are based on the silicon-on-insulator (SOI) technology. In this article, a bulk version of FED (BFED) is proposed for the first time. Both SOI-FED and BFED are simulated using TCAD tools as a semiconductor drift-diffusion solver. The proposed bulk FED can operate as well as a regular SOI-FED. Most sensitive parameters in the design of the BFED are doping and thickness of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{p}^{+}$ </tex-math></inline-formula> -drain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> -source. The effect of these parameters is investigated on the output characteristics of the BFED.

Modeling of Double-Gate Field-Effect Diodes for Analog Applications

As technological trends impose device dimension limitations, exploring other devices apart from metal oxide semiconductor field effect transistor, due to short-channel effects, has become inevitable. Higher ION/IOFF ratios and faster switching rates are quintessential characteristics for nanoelectronics. A field effect diode (FED) is one such device that exhibits greater drive current and low leakages when compared to silicon on insulator technology. Also, the FED fabrication process is compatible with complimentrary metal oxide semiconductor technology. Recently, several approaches have been proposed to tackle the low OFF current problem in FED such as Modified—FED and Side—Contacted FED. The FED structure proposed here is also believed to exhibit lesser short-channel effects, smaller OFF-state current, and higher ON-state current than a regular FED structure. We have explored the possible effects of material variation and work function engineering in our structure. Comprehensive analysis of the proposed device has also been done on some figures of merit such as subthreshold slope, energy-delay product, intrinsic gate delay, etc. thereby making this device suitable for electrostatic-discharge protection. Our numerical investigation promises FED’s efficacy in future logic applications in the nanometre regime.

The Novel Structure to Enhancement Ion /Ioff Ratio Based on Field Effect Diode

This paper proposes a new structure named a Side Contact lateral Doping Field Effect Diode (SLFED) to overcome the short channel effects of a regular field effect diode (FED). The fabrication of this new structure is simple that can be fabricated by the standard CMOS process technology, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs has presented. Our results show that the calculated I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio is several orders of magnitude larger than of the regular FED. For simulating the structures, we have applied semiconductor device simulation tools.

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Capacitance–resistance modeling of an inverter based on a nanoscale side-contacted field-effect diode with an overshoot suppression approach

Performance Improvement of Nanoscale Field Effect Diode (FED) with Modified Charge Channel: 2D Simulation and an Analytical Surface Potential Model

Performance Improvement of Nanoscale Field Effect Diode (FED) with Modified Charge Channel: 2D Simulation and an Analytical Surface Potential Model

Noise-Immune 6T SRAM Bit-Cells Based on Side-Contacted FED

Modern system-on-chip (SoC) designers are trying to include more considerations in designing building blocks to present reliable integrated digital circuits as well as high-density ones. In this article, an innovative static random access memory (SRAM) bit-cell architecture is successfully designed based on the previously proposed side-contacted field effect diode (S-FED) using 180-nm technology. The device structure is optimized to satisfy high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio more than seven orders of magnitude. Behavioral modeling of S-FED in comparison with CMOS counterpart provides the capability of employing S-FED in the pull-down, pull-up, and pass-gate networks with identical geometry. The simplest triple S-FED-based bit-cell is designed to evaluate write and read logic 0/1 operations utilizing steady-state responses. Transient and ac analysis are also extracted from the six S-FED-based bit-cell to characterize SRAM fingerprints. Results demonstrate that the proposed bit-cell is noise-immune with maximum static noise margin (SNM) equal to 33.6% V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , high-speed with switching frequency of about 1.8 GHz (write) and 50 MHz (read), and low-power with static and dynamic power consumption lower than 10 nW and 5 nW/GHz, respectively. Moreover, SNM and Monte Carlo (MC) analyses reveal outstanding stability of the designed SRAM bit-cell based on S-FEDs when extreme variability scenarios induce device degradation.

Numerical solution of the Schrödinger equation in nanoscale side-contacted FED applying the finite-difference method

Numerical approaches play an outstanding role in solution of quantum mechanical problems with due attention to the complexity of analytic solutions for open systems. This paper studies quantum characteristics of the previously proposed side-contacted field-effect diode (S-FED) as an emerging device in the modern system-on-chips (SoCs) using the finite-difference method (FDM). The characteristics obtained by solving the Schrödinger equation and regarding the distinguished potentials in ON and OFF states include energy levels and time-independent/dependent wave functions. The cosine dependency of eigenvalues on longitudinal position conveys level broadening in high states stringing a sequence of probability oscillations in the ON state. Remarkable potential barriers in the OFF state result in an inability of electron movement from source to drain in low energies; nevertheless, by overcoming the total energy to potential barrier, the transport is feasible in higher states, so that minority carriers contribute to transport mechanism in the highest energies.

Performance comparison of 6T SRAM bit-cells based on side-contacted FED and CMOS

Designing a Static Random-Access Memory (SRAM) cell configuration that copes with conventional complementary metal-oxide-semiconductor (CMOS) constraints on the cell area is desired to satisfy high packing density in integrated digital circuits. This paper analyzes and compares performance parameters of 6T SRAM bit-cells based on the side-contacted field-effect diode (S-FED) and conventional CMOS at 180 nm technology node. Steady-state responses demonstrate that in the worst-case, by applying weak logic 0/1 to the bit-lines, strong logic data is stored in the S-FED-based cell with superior write margin and lower power consumption by about one order of magnitude in comparison with the CMOS-based one. Comparing static noise margin reveals that S-FED-based cells enjoy prominent stability, especially in the read and hold operations with ~3X and 29% improvements, respectively, to the CMOS-based versions. In addition, enhancement of read-stability is attained utilizing S-FED-based cell, as well as decrement of subthreshold current and static power dissipation, compared with the CMOS-based one. Sensitivity analyses extracted from Monte Carlo simulations and butterfly curves indicate that S-FED-based cell successfully tolerates process and supply voltage variations in all operation modes, superior to the CMOS-based counterpart.

Design and simulation of high-performance 2:1 multiplexer based on side-contacted FED

Designing a high-quality switch block ensures the efficient data transmission in digital circuits and systems. In this paper, an innovative 2:1 multiplexer is successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs) at 180 nm SOI technology node. Optimization of the reservoir thickness and gate work function of the S-FED satisfy high ION/IOFF ratio and noise-immunity. DC, AC, and transient mixed-mode simulations are employed to scrutinize and compare performance of constituent logic gates based on the S-FED and CMOS. Simulation results demonstrate superior noise margins up to 100 mV for the S-FED-based inverter compared with the CMOS-based counterpart. Furthermore, the S-FED-based transmission gate with switching frequency of 38.9 GHz can act as a high-speed alternative for the CMOS-based one. Both multiplexer architectures configured by the S-FED and CMOS are compared in terms of performance parameters. In this regard, average power consumption and PDP quantities for the S-FED-based multiplexer reveal significant reductions by about 2 and 3 orders of magnitude, respectively, compared with the CMOS-based one. In addition, propagation delay time increases drastically with scaling power supply in the CMOS-based multiplexer; while, this increase is suppressed for the S-FED-based version.

A monolithic integration scheme for GaN-based power converter integrated circuit using fully-Schottky versatile HEMTs

A monolithic integration scheme for GaN-based power converter integrated circuit is proposed in this paper, wherein the scheme is based on a novel versatile HEMT architecture featuring full-Schottky contacts. By simply introducing only one type of device for building both field effect transistors and diodes, the power converter ICs could be realized in a compact way. In addition, this scheme avoids harmful high temperature process which is for forming ohmic contacts in some nitride semiconductors. In this sense, this scheme could significantly reduce the complexity of the integration, and therefore, promisingly enable higher device performance.

Double-Gate Field-Effect Diode: A Novel Device for Improving Digital-and-Analog Performance

In this article, a novel double-gate (DG) field-effect diode (FED) has been proposed, which exhibits smaller short-channel effects (SCEs), smaller OFF-state current ( $I_{\mathrm{\scriptscriptstyle OFF}}$ ) and higher ON-state current ( $I_{\mathrm{\scriptscriptstyle ON}}$ ) compared with the previously introduced common FEDs and the side-contacted FEDs (SFEDs). Based on the TCAD simulation study, due to the stronger control of the two gates over the channel, the proposed double-gate FED (DGFED) is shown to suppress the SCEs and to improve $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ ratio significantly compared with the SFEDs. The proposed device is also shown to have smaller gate delay time, smaller energy-delay product, larger cutoff frequency, and larger transconductance than the SFED. Thus, DGFED is a promising device for substituting the SFED in possible high-frequency analog and digital applications.