Field Effect Diode Research Articles

4-Azafluorenone and α-Carboline Fluorophores with Green and Violet/Blue Emission.

The emission properties of three 4-azafluorenone and five new α-carboline fluorophores in both solution and thin solid films were investigated. Fluorescence of the azafluorenone is clearly enhanced in thin solid films due to the presence of phenyl/biphenyl rotors, and these derivatives can be classified as green Aggregation-Induced Emission luminogens (AIEgens) with a non-emissive heteroaromatic core structure. Compared to azafluorenones, emission of α-carbolines is hypsochromically shifted to the blue region of the electromagnetic spectrum, and most of these derivatives exhibit strong violet-blue fluorescence in both solution and thin solid film layers. Further, the effective mobility and electroluminescence of new α-carbolines were investigated in prepared organic field-effect transistors and organic light-emitting diodes, respectively.

Improved nanoscale field effect diode

To overcome the short channel effects of a regular field effect diode (FED), this paper proposes a novel nanoscale FED. The novel FED has a simple structure that can be fabricated by the standard CMOS process technology. Both regular and novel FEDs are simulated using TCAD tools as a semiconductor drift-diffusion solver. Simulation results show that the novel device can operate properly at nanoscale channel length. The I ON/I OFF ratio of the novel FED is several orders of magnitude higher than of the regular FED.

Nanoscale field effect diode (FED) with improved speed and I ON / I OFF ratio

Field effect diodes (FEDs) are devices that have higher ON current and lower OFF current compared to metal oxide semiconductor field effect transistors in similar dimensions. The modified FED and side contacted FED (S-FED) structures do not turn off for 40 nm channel lengths and shorter by considering the band-to-band tunnelling model. In this study, a new structure of FED with a 25 nm channel is presented. In this structure, the use of isolating oxides and reservoirs in the channel causes improvement in the structural compared to the conventional FED structures. The proposed techniques reduce the tunnelling in the channel. The simulations have been done by using Silvaco TCAD. In the proposed structure, the results show that the OFF current and gate delay are decreased from 1.5 mA to 66.5 nA and 0.103 to 0.033 ps, respectively. Also, compared with the S-FED structure by considering the band-to-band tunnelling model, the knee voltage for the length of the 25 nm channel dropped from 0.8 to 0.4 volts. Furthermore, the I ON / I OFF ratio, which is an important parameter in digital applications, dramatically increases to a magnitude of 10 5 .

Performance Evaluation of Innovative Ion-Sensitive Field Effect Diode for pH Sensing

In this paper, we have successfully introduced and characterized an innovative ion sensitive device called “Ion sensitive field effect diode”, a completely new ion-sensitive sensor. In conventional ion-sensitive devices, electrolyte/insulator interface reactions produce a conductive channel between the drain and the source whereas in our proposed structure, a p-n junction forms and is responsible for the conductivity. Since it is for the first time that such device is proposed as an ion sensor, comprehensive characterizations have been performed based on our previously TCAD-based model which was developed to simulate electrolyte and electrolyte/insulator interface. Considering this reliable model, sensing parameters of pH sensors, such as sensitivity and signal to noise ratio are investigated and evaluated. Meanwhile, an accurate model to approximate the noise behavior of the device is proposed. Moreover, the effect of Silicon active layer thickness and doping concentration on the sensitivity of the device has been studied. Results reveal that ion sensitive field effect diode can achieve sensitivity about five times higher than the Nernst limit and can be considered as a promising candidate toward accurate and more sensitive ion sensors and this new type of sensor deserves further attention and development.

Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trigger voltage of 17 V, and a strong ESD robustness of 6000 V in an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1600~\mu \text{m}^{\textsf {2}}$ </tex-math></inline-formula> , benefitting from the gate-controlled field effect diodes and the weakened regenerative feedback of the SCR. As such, the proposed GDTSCR is an attractive device for constructing effective and latch-up immune solutions for HV ESD protection.

Junctionless Field Effect Diode (JL-FED): A First-Principles Study

This paper proposes a novel field effect diode (FED) for the first time namely junctionless FED (JL-FED). Our simulation results show that JL-FED gives the combined advantages of conventional FED and JL field effect transistor (JL-FET). In fact, not only fabrication process of the JL-FED is easier than FED, but also unlike a FED, JL-FED device turns on without applied biases to the control gates. Furthermore, to reduce the leakage current of the JL-FED structure, we propose modified JL-FED (MJL-FED) structure, in which the control gates work functions are different from that of JL-FED. The digital performance parameters such as ION/IOFF ratio and subthreshold slope (SS) for MJL-FED are investigated using 2-D simulations. MJL-FED offers superior ION/IOFF ratio and SS than its JL-FED counterpart having same dimensions. Our simulation results show that MJL-FED provides channel length scaling possible down to 10 nm, and it is a reasonable candidate for logic transistor applications.

Synthesis, characterization, and hole-transporting properties of benzotriazatruxene derivatives

Four derivatives of benzotriazatruxene are synthesized and tested as hole-transporting materials in organic field-effect transistors and organic light-emitting diodes.

Programmable negative differential resistance device using FED

A novel programmable negative differential resistance (NDR) device based on the field-effect diode is proposed. The field-effect diode (FED) is a gated diode and compatible with semiconductor on insulator (SOI) CMOS technology. Semiconductor device simulator tools are used to simulate the structure of the FED. Then, it is employed to design the programmable NDR device. The operating principles of this new device are similar to the comparable MOSFET device. The proposed design is a unique device that consists of only three transistors and can be programmed by an isolated gate.

Impact of scaling voltage and size on the performance of Side-contacted Field Effect Diode

Side-contacted Fild Effect Diode (S-FED), with low leakage current and high Ion/Ioff ratio, has been recently introduced to suppress short channel effects in nanoscale regime. The voltage and size scalability of S-FEDs and effects on the power consumption, propagation delay time, and power delay product have been studied in this article. The most attractive properties are related to channel length to channel thickness ratio in the S-FED which reduces in comparison with MOSFET significantly, while gates control over the channel improve and the off-state current reduces dramatically. This promising advantage is not only capable to improve important S-FED's characteristics such as subthreshold slope but also eliminate Latch-up and floating body effect.

Graphene-based Field Effect Diode

One of the major problems with Graphene transistors is the small On/Off current ratio. In spite of introducing various methods to improve this problem, like patterning the Graphene layer or using the Graphene nanoribbons, this issue still limits the use of Graphene transistors. Here, we present a new Graphene-based, 4-terminal device and discuss its application as a Graphene-based transistors. The proposed structure is a Filed Effect Diode (FED) in which Graphene acts as the channel. In the structure of Graphene-Field Effect Diode (G-FED), two gates are located over the channel and biased oppositively to electrically induce n or p regions in Graphene layer. As the Off current of G-FED is limited to only the leakage current of a reverse-biased diode, the On/Off current ratio is large in comparison with the comparable Graphene Filed effect Transistor (G-FET). We have measured the current-voltage curves of G-FED as well as the carrier concentration and energy band diagram in both On and Off states. It has been observed that G-FED performance is similar to a silicon-based FED with rectifying characteristics. We have demonstrated that the On/Off current ratio obtained for the G-FED is about 100 while this value is less than 15 for the G-FET with the same dimensions. Additionally, the G-FED has the same fabrication process as the G-FET and no difficulty is needed for patterning the Graphene layer to get the high On/Off current ratio. This demonstration reveals the great potential of Graphene-based Field Effect Diode in digital nanoelectronics applications as well as analog mixers.

Dual material gate nanowire field effect diode (DMG-NWFED): Operating principle and properties

In this paper the impacts of warp-around gates on the electrical characteristics of a field effect diode (FED) have been presented in terms of ION/IOFF ratio and gate delay by a numerical simulator. Simulation results show that quantum confinement effects result in nanowire regular FED (NWRFED) does not meet the drive current requirements predicted by the international technology roadmap for semiconductors (ITRS). By employing the gates with a different workfunction, we propose a “dual material gate nanowire FED (DMG- NWFED)” structure which supports the drive current requirements predicted by ITRS. Numerical simulations show that the subthreshold slope (SS) of the proposed structure is 53 mV/dec. In addition, the ION/IOFF ratio in DMG-NWFED is approximately thirteen orders of magnitude bigger than ION/IOFF ratio in NWRFED. The proposed structure provides a negative differential resistance (NDR) characteristic for 7.5 nm channel length and 3 nm nanowire diameter. This perhaps renders DMG-NWFED a prominent candidate for multilevel digital circuit applications due to its NDR characteristic.

An innovative ion sensitive device based on side‐contacted field effect diode

In this paper, side‐contacted field effect diode as an ion sensitive device is proposed to take advantages of field effect diodes family in sensing ionic species in solutions. To analyze the behavior of ion sensitive side‐contacted field effect diode, an accurate model has been developed in a simulation environment tool to mimic the characteristics of the solution and the results compared with the literature. While dual gate ion sensitive FETs have been introduced to beat the Nernst limit, results show that dual gate ion sensitive side‐contacted field effect diodes can provide better performance. Effects of various parameters such as silicon body thickness and doping concentration have been studied. In contrast of ISFETs, the proposed device offers more sensitivity at the thicker silicon body. Results indicate that dual gate ion sensitive side‐contacted field effect diodes can be regarded as an interesting candidate for bio‐sensing applications.

An AlGaN/GaN field effect diode with a high turn‐on voltage controllability

In this paper, an AlGaN/GaN Field Effect Diode (FED) with high turn-on voltage (VON) controllability is proposed. The structural feature of a δ-doped GaN cap, an AlGaN barrier, and a GaN channel (GaN/AlGaN/GaN), and selective dry-etching of the GaN cap, ensure the precise control of VON which can be modulated by AlGaN barrier layer thickness. The VON as low as 0.3 V is obtained at the remained AlGaN thickness of 4-nm with an extremely low estimated VON deviation.

The role of chain conformation in energy transfer properties of single conjugated polymer molecule

Study of the relationship between conformation and photophysics of individual -conjugated polymer chain is one of the most important problems in polymer nanoscience and nanotechnology, which will facilitate the application of conjugated polymer in a range of electronic devices such as organic field-effect transistors, light-emitting diodes, and solar cells. Single-molecule spectroscopy has emerged as a powerful tool to unravel structure and dynamic heterogeneities that are hidden in ensemble average. Identification of the emitting segments through fluorescence of single conjugated polymer molecules and their dependence on the conformation can help reveal the mechanism and the extent of energy transfer process in a single polymer chain. In this paper, the photophysical properties of individual poly[2, 7-(9, 9-dioctylfluorene)-alt-4, 7-bis(thiophen-2-yl) benzo-2, 1, 3-thiadiazole] (PFO-DBT) conjugated polymer molecules are measured based on the defocused wide-field microscopy of single molecules. The single PFO-DBT molecules are prepared on cleaned glass coverslips by spin-coating solution of poly[methyl methacrylate] (PMMA) containing 110-9 mol/L PFO-DBT molecules in chloroform and toluene, respectively. Defocused imaging of single conjugated polymer molecule is performed based on a wide-field fluorescence microscope system. The change of defocused patterns of individual polymer chain maps the angular distribution of emitted chromophore and thus the emitting dipole orientation. Fluorescence trajectory and corresponding emission dipole moments of single conjugated polymer molecules are analyzed to identify the emitting conjugated segments. It is found that single PFO-DBT conjugated polymer molecules prepared by chloroform solvent show extended conformation. The intrachain energy transfer is dominant in the single conjugated polymer molecules that take extended conformation, which leads to photophysical properties of multiple chromophores. In contrast, single PFO-DBT conjugated polymer molecules prepared by toluene solvent hold folded conformation, which exhibit emission from single chromophore due to efficient interchain energy transfer. The emitting chromophore is not constant in a single PFO-DBT conjugated polymer molecule with folded conformation. About 35% of the single conjugated molecules prepared with toluene show only one constant emitting chromophore before photobleaching. However, about 65% of single conjugated polymer molecules prepared with toluene show two or more sequencely emitting chromophores. It can be concluded that the energy transfer properties of single PFO-DBT conjugated polymer molecule is greatly dependent on the conformation, which can be reflected in its photophysical properties. The study on the influence of single conjugated polymer conformation on energy transfer efficiency can provide the reference for the preparation and performance of optoelectronic devices and molecular devices based on conjugated polymer.

Design and Simulation of Low-Power Logic Gates Based on Nanoscale Side-Contacted FED

A new nanoscale device has been already introduced as a side-contacted field effect diode (S-FED), which is composed of a diode and planar SOI-MOSFET. In this paper, S-FED is optimized in terms of work function, with due attention to the design of logic gates, such as NOT, NAND, NOR, and XOR. Results demonstrate that optimum work function is 4.7 eV in which the highest value of $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ can be achieved. Mixed-mode simulations are used to determine the performance of the proposed logic gates. Also, the proof regarding the mitigation of the total power consumption up to 56% is presented so that not gate based on S-FED improves power delay product by about 30%, compared with the CMOS-based version. A similar fabrication process with the CMOS technology could be asserted as the considerable advantage to pave the way of feasibly realizing the new generation of S-FED-based logic gates.

Improving gate delay and I ON/I OFF in nanoscale heterostructure field effect diode (H-FED) by using heavy doped layers in the channel

This paper explores the effects of biaxial tensile strain on the electrical characteristics of the field effect diode (FED) in nanometer regime. The FED current directly depends on carrier mobility in the channel. By employing germanium in the channel, carrier mobility is enhanced and accordingly the derive current is increased. We propose a new structure, namely heterostructure FED (H-FED). The proposed structure does not turn off for channel lengths shorter than 75 nm. We also propose a second new structure called modified H-FED (MH-FFD) to improve the electrical characteristics of H-FED by using the silicon germanium in the source and drain regions, as well as a doped-silicon layer in the channel. Furthermore, we demonstrate that for channel lengths shorter than 40 nm, the side-contacted FED (S-FED) device does not turn off, whereas the proposed structure makes device channel length scaling possible down to 25 nm. The simulation results show that for a 45-nm channel length, the MH-FED gate delay is improved by 40 % and the energy delay product by 35 %, as compared to those of the S-FED. The I ON/I OFF ratio for the MH-FED at channel lengths larger than 60 nm is at least five orders of magnitude higher than that in the S-FED.

An Inverter Gate Design Based on Nanoscale S-FED as a Function of Reservoir Thickness

In this paper, an inverter logic gate has been successfully designed based on the previously proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the S-FED performance is investigated, and then the output characteristics of the S-FED-based inverter are studied and compared with those of the existing CMOS technology. The S-FED performance evaluation is performed in terms of important figures of merit for logic application in various reservoir thicknesses, including transconductance, intrinsic gate delay time, energy delay product, and subthreshold slope. The numerical results demonstrate that the optimum reservoir thickness is 7 nm, and the threshold voltage can be controlled by reservoir thickness. Mixed-mode simulations also indicate that, in the design of an inverter utilizing S-FEDs, the delay and the power dissipation of the logic gate are reduced. These results indicate that the S-FED can be an interesting candidate for designing low-power and high-speed logic gates.

SOI FED-SRAM Cell: Structure and Operation

A static memory cell (SRAM) based on the field-effect diode (FED) is presented, and its operation is explained with the help of numerical device simulations. Although this new cell resembles the thin-capacitively coupled-thyristor (TCCT) SRAM cell in concept and operation, it is nevertheless characterized by significant advantages. These advantages derive from the fact that the thyristorlike mode of operation of the FED is gate induced, whereas the TCCT is an actual built-in thyristor. The operation of the cell is explained with the help of suitable timing diagrams, and the mechanisms of storing 1 and 0 are analyzed with detailed numerical simulations. In one operation scheme (where the cell could better be termed quasi-SRAM), a sequence of restore pulses is periodically applied after the cell is put on Hold, which ensures that the stored data remain valid for as long as the cell is powered ON. High read 0/1 current margin, fast write/read time, and densely packed cells are among the cell advantages obtained.

Multi-Timescale Microscopic Theory for Radiation Degradation of Electronic and Optoelectronic Devices

A multi-timescale hybrid model is proposed to study microscopically the degraded performance of electronic devices, covering three individual stages of radiation effects studies, including ultra-fast displacement cascade, intermediate defect stabilization and cluster formation, as well as slow defect reaction and migration. Realistic interatomic potentials are employed in molecular-dynamics calculations for the first two stages up to 100 ns as well as for the system composed of layers with thicknesses of hundreds of times the lattice constant. These quasi-steady-state results for individual layers are input into a rate-diffusion theory as initial conditions to calculate the steady-state distribution of point defects in a mesoscopic-scale layered-structure system, including planar biased dislocation loops and spherical neutral voids, on a much longer time scale. Assisted by the density-functional theory for specifying electronic properties of point defects, the resulting spatial distributions of these defects and clusters are taken into account in studying the degradation of electronic and optoelectronic devices, e.g., carrier momentum-relaxation time, defect-mediated non-radiative recombination, defect-assisted tunneling of electrons and defect or charged-defect Raman scattering as well. Such theoretical studies are expected to be crucial in fully understanding the physical mechanism for identifying defect species, performance degradations in field-effect transistors, photo-detectors, light-emitting diodes and solar cells and in the development of effective mitigation methods during their microscopic structure design stages.

Excellent scalability including self-heating phenomena of vertical-channel field-effect-diode type capacitor-less one transistor dynamic random access memory cell

The scalability study and the impact of the self-heating effect (SHE) on memory operation of the bulk vertical-channel field effect diode (FED) type capacitorless one transistor (1T) dynamic random access memory (DRAM) cell are investigated via device simulator for the first time. The vertical-channel FED type 1T-DRAM cell shows the excellent hold characteristics (100 ms at 358 K of ambient temperature) with large enough read current margin (1 µA/cell) even when silicon pillar diameter (D) is scaled down from 20 to 12 nm. It is also shown that by employing the vertical-channel FED type, maximum lattice temperature in the memory cell due to SHE () can be suppressed to a negligible small value and only reach 300.6 from 300 K ambient temperature due to the low lateral electric field, while the vertical-channel bipolar junction transistor (BJT) type 1T-DRAM shows significant SHE ( K). Moreover, this excellent thermal characteristic can be maintained even when D is scaled down from 20 to 12 nm.