FET Structure Research Articles

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential, in addition to electric field of triple-material double-gate (TMDG) tunnel FET. The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source. The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage, lateral and vertical electric field. Because the TMDG TFET has a simple compact structure, the surface potential is computationally efficient and, therefore, may be utilized to analyze and characterize the gate-controlled devices. Furthermore, using Kane's model, the current across the drain can be modeled. The graph results achieved from this device model are close to the data collected from the technology computer aided design (TCAD) simulation.

Modeling and Circuit Design of Associative Memories With Spin–Orbit Torque FETs

This article introduces a circuits model for a proposed spin-based device called a spin–orbit torque field-effect transistor (SOTFET) that can operate as a nonvolatile memory and logic device. The SOTFET utilizes an FET structure with a ferromagnetic-multiferroic (MF) gate-stack that enables read/compute and write functions to be isolated. This is achieved by a combination of a ferromagnetic layer that is programmable via spin–orbit torque coupled to an MF layer that also couples into the gate of a traditional FET. Additionally, this device has logic gate-like behavior and can be designed to operate in either AND or OR gate mode. We begin with a physics-based model of this device and derive a SPICE level model that can be integrated into the Cadence toolset. Using such a device we demonstrate MRAM, content addressable memories (CAM), and ternary CAM (TCAM) functionality with 3 to 5 transistors, a significant decrease over the CMOS alternative circuits, showing that such a device can enable low cost and compact associative memories not currently feasible with CMOS devices.

Thickness‐Dependent Electronic Transport in Ultrathin, Single Crystalline Silicon Nanomembranes

Adv. Electron. Mater., 2019, 5, 1900232 Some errors were present in the figure captions of this manuscript. The correction captions are reproduced below. Figure 1. Ultrathin Si-NM reduction process and corresponding characteristics. A) Schematic of our HF treatment process: thermal oxidation under 90% ozone atmosphere for 12 min at room temperature and stripping the oxide using 10% HF solution for 90 s. After 26 cycles, the thickness of Si-NM sample can be thinned from 50 to 10 nm. B) High-resolution TEM image of HF-thinned Si-NM. Inset is a corresponding diffraction spectroscopy image, indicating little surface reconstruction. C) High-resolution TEM of a 10 nm thick Si-NM. Figure 2. Basic electrical performance based on 10 nm thick Si-NM FETs. A) Schematic of the Si-NM FET structure. "Inset is a colorized optical microscope image of a Si-NM device (channel length L = 5 µm, width W = 10 µm) with the electrode area colored yellow. B) |IDS|–VDS curve at room temperature when VG is fixed at 1 V in a 10 nm thick Si-NM FET. Gate leakage current is plotted by black dots. C) Transfer characteristics of the Si-NM FET. Along the direction of the arrows, VDS changes by steps of 1 V. D) Band profiles of Si-NM FETs at various source-drain biases when VDS = 0, < 0, and > 0. Figure 3. The temperature-dependent property and analysis of Si-NM FETs with various thickness. A) Temperature-dependent IDS–VDS measurement of a 10 nm thick Si-NM FET when gate voltage VG is fixed at 0 V. B) Temperature-dependent conductivity of different thickness Si-NM. C) Re-plot of (B) using lnσ versus T−1/4 coordinates, where blue line shows acceptable linear fitting of 50 nm Si-NM data and others show obvious deviation from linear relationship. D) Re-plotted temperature-dependent conductivity of 10 nm thick Si-NM with lnσ versus lnT coordinate. Red and yellow dash line shows best linear fitting with T−η, η ≈ 0.5, and T3/2, respectively. The gray dash line shows an increasing tendency of conductivity for bulk p-doped semiconductor. E) Conductivity as a function of thickness at different temperatures (50 K, 100 K, 200 K and 300 K). The dots are experimental data and the solid line is a fitted curve. σ0 is the conductivity of 50-nm-thick Si-NM at each temperature.

Influence of Source Stack and Heterogeneous Gate Dielectric on Band to Band Tunneling Rate of Tunnel FET

In this paper, the presence of source stack and heterogeneous gate dielectric material in the structure of an n-channel tunnel FET (TFET) is investigated. P+ type source stack above the source region causes an increase in the electric field which in turn leads to more band bending in the energy band diagram of the proposed structure. Therefore, the effective width of tunneling region decreases and as a result electron Band to Band Tunneling (BTBT) rate enhances. It is also shown that incorporating hetero gate dielectric material can further enhance BTBT rate in the source-channel region and it becomes more intensive as the permittivity of high-k dielectric is increased. The hetero gate structure which is utilized is a combination of SiO2 and a high-k material. Our simulation results indicate that the presence of SiO2 in the drain side minimizes ambipolar current at negative gate voltages. Simulations are performed using Silvaco Atlas TCAD for a channel length of 50 nm using nonlocal tunneling model.

Features of Electrophysical Diagnostics of Schottky Field Transistors Based on GaAs Epitaxial Layers on Silicon Substrates for Microsystem Applications

In this paper, the structure of GaAs FET on a silicon substrate, suitable for local integration in the local SOI technology and the method of its electrophysical diagnostics based on changes in the thermal resistance (RT), is analyzed. It is known that the thermal conductivity of GaAs is 3-4 times worse than silicon. To eliminate this disadvantage, the technology of forming high-speed GaAs-structures on the surface of the silicon substrate was propoused.

Regrown source/drain in InGaAs multi-gate MOSFETs

To realize further progress in the field of integrated circuits, a high mobility channel material, such as InGaAs for n-MOSFETs, with a multi-gate structure is desired. To realize high current densities in InGaAs MOSFETs, heavily doped sources/drains obtained using epitaxial growth are required. Here, we report the regrowth of source/drain using MOVPE for fin FET and nanosheet FET structures. A thinner flow liner for higher flow rate of 1.5 m/s was selected as a growth condition to improve the selective growth property and contact characteristics. As a result, a carrier concentration of 2 × 1019 cm−3 and contact resistivity of 8.0 × 10−8 Ωcm2 were obtained simultaneously.We fabricated fin FET and nanosheet structures as multi-gate MOSFETs. In the case of fin FETs, the surrounded growth of the channel and operation of a 16-nm-gate device were confirmed. In the case of nanosheet FETs, we used butt-jointed structures, i.e., we performed regrowth after the channel portion was formed into a mesa shape by etching, and the regrowth interface was a boundary between the channel and source/drain. After the regrowth and removal of the InP layer between the sheets, it was confirmed that the two layers of the nanosheets were supported by the regrown source/drain layers on both sides. In this structure, the operation of the 40-nm-gate device was also confirmed.

Two dimensional Green's function solution of threshold for junction less field effect transistors at low drain voltage

The threshold voltage is an important device and circuit parameter of any FET structure. In this paper, closed form analytic expressions are derived which determine the dependence of the threshold voltage of DGJLFETs on device dimensions, and the drain voltage. The depletion approximation and the two dimensional Green's function are used to determine the terminal behavior of the device. The model includes the effect of the depletion in the gate-drain spacing. The threshold condition is reached when the depletion layers from the two sides cross i.e., when the channel pinches off. The widening of the depletion layer under sub-threshold condition, and the movement of the pinch-off point with the drain voltage are calculated. Finally, the shift in threshold voltage and DIBL with the gate length is determined. We can also determine the potential distribution within the device. To verify our calculations, the analytical results are compared with 2-D numerical simulations. The agreement is especially good at low drain voltages.

(Invited) Nanostructured Materials Based Sensors for Smart and Wearable Electronics

Smart and wearable electronic systems are promising for personal healthcare in near future. For smart health technology, various sensor-integrated portable, mobile and wearable systems have been extensively developed. Recently many sensor devices are being integrated into smartphone, which enables analysis of biomarkers from various body fluids and monitoring of physiological parameters. And many wearable sensor-integrated systems including skin-attachable platform which can monitor physiological signs, detect biomarkers for disease diagnosis and monitor the patients with chronic diseases have been extensively investigated. Here, I will discuss imaging-based fluorescence biosensors for highly sensitive detection of biomolecules and pathogenic bacteria which can be integrated with smartphone or portable IOT systems. In addition, I will present our recent works on stretchable wearable physical sensors (strain, pressure, and temperature), chemical sensors (gas) and biosensors (metabolite, protein) based on low-dimensional nanoscale materials (0D, 1D and 2D), nanocomposites or their hierarchical nanohybrids in FET, resistor or electrochemical device structures. Finally, future prospects in the development of the sensors for smart healthcare will be discussed.

(Invited) Growth and Characterization of GaN Based Multi-Channel FETs

With recent advances in new device architectures such as FIN FETs, Super-Lattice Castellated Field Effect Transistors (SLCFET), and buried dual gate FETs (BRIDGE FET), there is more and more advantages for GaN based multiple channel FETs. By simply increasing the number of channels, the Ns can be increased to several times higher than a single channel device. However, the maximum number of the channels is largely limited by the tensile stress in the AlGaN/GaN materials system. By optimizing the growth conditions and delta doping, we have achieved a sheet resistance as low as 21 Ohm/sq in a 16-channel FET structure. We also found that, by controlling the delta doping, the sheet resistance is linearly scaled with the number of channels.

Design structure of tunnel FET by combining thermionic emission with tunneling phenomenon

This study proposes a novel electrically doped tunnel field effect transistor (ED-TFET), which combines thermionic emission and band to band tunnelling by using an additional metal source (MS) of appropriate work function (WF; 3.9 eV) by forming an ohmic junction between metal and silicon. The ohmic junction is created below the channel region near the source channel junction by depositing of appropriate workfunction metal (lower than silicon) which injects extra electrons through over the barrier along with band to band tunneling (BTBT) in the channel of the device. Therefore, a drastic improvement in the ON state current is observed which is numerically about 107 times greater than conventional ED-TFET. Furthermore, the radiofrequency figures of merit such cut-off frequency, gain band width product, and maximum oscillating frequency are enhanced by ~10 6 , 20 and 1000 times, respectively, however, intrinsic gain and transconductance generation factor have nearly 66.66 and 14.28% improvement compared to conventional ED-TFET. Furthermore, the concepts of drain underlapping and dual metal gate have been used to checkout OFF-state current and negative conductance as a final proposal. In addition, this study has also investigated the performance variations in the proposed structure due to the WF change of CG2, length of L D1 and position of MS.

Trap and 1/f-noise effects at the surface and core of GaN nanowire gate-all-around FET structure

Using capacitance, conductance and noise measurements, we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1D) array of GaN nanowire gate-all-around field effect transistor (GAA FET), fabricated via a top-down process. The surface traps in such a low dimensional device play a crucial role in determining the device performance. The estimated surface trap density rapidly decreases with increasing frequency, ranging from 6.07 × 1012 cm−2·eV−1 at 1 kHz to 1.90 × 1011 cm−2·eV−1 at 1 MHz, respectively. The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (Vgs > Vth = 3.4 V) for all frquencies. In the surface depletion region (1.5 V < Vgs < Vth), the device is governed by 1/f at lower frequencies and 1/f2 noise at frequencies higher than ~ 5 kHz. The 1/f2 noise characteristics is attributed to additional generation–recombination (G–R), mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire. The cutoff frequency for the 1/f2 noise characteristics further shifts to lower frequency of 102–103 Hz when the device operates in deep-subthreshold region (Vgs < 1.5 V). In this regime, the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G–R noise prevails in the entire nanowire channel.

28 GHz GaAs pHEMT MMICs and RF front‐end module for 5G communication systems

AbstractThis article presents a 28 GHz switch and LNA chipset, and the RF front‐end module for 5G communication systems. The 28 GHz Single Pole Double Through (SPDT) switch and LNA MMICs are embedded in single RF front‐end module successfully using molding based embedded Wafer‐Level Package (eWLP) technology. For the low noise figure and high isolation, inductive source degenerated LNA topology and double shunt FET structure for SPDT switch are employed, and LNA and SPDT are implemented in single IC. The eWLP based package minimizes the parasitic component such as bond‐wire inductance and signals loss to enhance the performance of the RF front‐end module. At 28 GHz, the measured gain and noise figure of receiver path are 15.5 dB and 3.46 dB, respectively, and the IIP3 is +3 dBm at 45 mW power consumption.

Insights Into the Impact of Pocket and Source Elevation in Vertical Gate Elevated Source Tunnel FET Structures

In this paper, we investigate a vertical gate-based elevated tunnel source (TS) FET structure with and without a vertical n+ pocket and compare its performance with a lateral p-n-i-n TS (LTS) FET. The lined arrangement of gate not only provides a performance boosting as expected but it further allows the flexibility to minimize the degradations at higher pocket doping using source elevation. The vertical gate and pocket alignment overcome the full-depletion constraint of the LTS FET and maintain a better subthreshold swing (SS) over a higher range of pocket doping and width. An optimized average SS as low as ~26 mV/dec is achieved over five decades of current which is improved by 58% and 67%, respectively, as compared to the LTS and p-i-n tunnel field-effect transistors (TFETs) with an on-current enhancement of one order and ~17×, respectively. Furthermore, the gate-to-drain capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> ) in elevated source structures is a highly sensitive function of the pocket doping and can be significantly reduced by tuning the source elevation length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CV</sub> at higher pocket doping. At the same pocket conditions, a one order reduction in C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> is achieved with respect to the lateral configuration without compromising the intrinsic delay (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> × V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ). The circuit-level investigations show that due to the, otherwise, higher C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GD</sub> in the LTS FET, the switching delay remains unaffected by the on-current boosting caused by higher pocket doping. However, it is drastically improved by ~23% in elevated source structures at a change from 4 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> to 5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . A faster switching delay(τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) of ~116 ps is achieved at a ~33% reduced device base area.

Hydrogen Peroxide Measurements by MISFET and LET Structures with Rear Porous Silicon Layer and Metallic Nanoparticles

In the paper hydrogen peroxide MISFET and LET sensor performance is investigated. As hydrogen peroxide is a product of many chemical reactions, especially biological reactions, peroxide sensors are now widely used for detection of another. In this work, a combination of two nanostructures that are now used for hydrogen peroxide detection – porous silicon and metal nanoparticles was used.A MISFET (metal-insulator-semiconductor field effect transistor) was chosen as the basic sensor but unlike conventional FET sensors sensitive area was formed on the rear side of the sensor. In the aim to simplify sensor structure a LET (light-effect transistor) with sensitive area on the rear side was also tested. LET structure was produced by the same technology as FET, but then subgate system was removed by chemical etching. Porous silicon was formed by metal-assisted chemical etching (MACE) that consists of two stages. During the first stage, metallic nanoparticles are deposited on the surface by chemical or physical deposition. During second one these particles become catalysts of chemical reaction and pores are formed under them. Pore shape and density depend on both stages conditions.Formation of porous silicon on the rear side leads to changes of substrate charge and influence gate-source curve as well as drain-source curve. Drain current for FET with an active area is lower due to the negative charge accumulated in porous silicon thanks to high tie connections concentration. Dependence of LET drain current on LED intensity (current) is almost linear and drain-source curves are similar to FET structure ones. FET samples with porous silicon/Pt and LET samples with porous silicon/Ag both show more stable and well-defined dependence of drain current on hydrogen peroxide concentration then samples without porous layer. All sensors have saturation of drain current from concentrations of hydrogen peroxide about 0.5-1% and dependence on concentration is first order exponential decay, obviously due to saturation of working area by reaction products or heating effect of hydrogen peroxide decomposition. In concentration range up to 0.3% hydrogen peroxide best sensitivity was demonstrated by LET sensor (574 μA/%), for FET sensor sensitivity is about 6 μA/% for MISFET without active area and about 8.3 μA/% for MISFET with active area. As Ag and Pt catalyst hydrogen peroxide decomposition, sensors with metal nanoparticles shows quicker reaction (maximum response less than in 3 minutes). To ensure accuracy and precision of measurements temperature and illumination of active area dependences of drain current should be taken into account. MISFET with porous silicon demonstrates typical for silicon structures exponential decay dependence of drain current on luminous flux and quasi-linear dependence on temperature Slopes are 34 μA/lm and 6.46 μA/˚C respectively.Hydrogen peroxide sensor with porous silicon shows good performance in both configuration – as MISFET and as LET structure. MISFET structure is more adjustable but have lower sensitivity (about 8 μA/% ) while LET structure is more simple and sensitive (up to 500 μA/% ). Use of both Ag and Pt nanoparticles decrease response time of sensor to 2-3 minutes.Ref 21, fig 17

Ferroelectricity of HfxZr1−xO2 Thin Films Fabricated Using TiN Stressor and ZrO2 Nucleation Techniques

Recently, HfxZr1−xO2 (HZO) thin films have been widely investigated to achieve low power device applications such as ferroelectric random access memory (FeRAM) and ferroelectric field effect transistor (FeFET), due to its stable ferroelectricity even in extremely thin region (~10 nm) and CMOS applicability [1]. Moreover, matured atomic layer deposition (ALD) techniques of HfO2 and ZrO2 enable the fabrication of three-dimensional structure required for future memory devices. TiN top- and bottom-electrodes (TE- and BE-TiN) are typically used as stressor layers to fabricate metal-ferroelectric-metal (MFM) capacitors with HZO films because TiN electrodes provide the mechanical stress required for the formation of the unstable ferroelectric orthorhombic phase [2]. However, this method is suitable only for MFM capacitors, cannot be applied to FET structures. On the other hand, in our previous research, the HZO film fabricated using a polycrystalline ZrO2 nucleation layer, inserted between the HZO film and the BE-TiN, results in the large remanent polarization (2P r = P r + − P r −) [3]. Therefore, the HZO film with top- and bottom-ZrO2 nucleation layers is expected to improve the ferroelectricity. In this study, we fabricated two types of MFM capacitors with HZO films crystallized using top- and bottom-TiN stressor layers and ZrO2 nucleation layers, and discuss the ferroelectricity and the leakage current (J) properties of two types of MFM capacitors. The TiN/ZrO2/HZO/ZrO2/TiN capacitors with top- and bottom-ZrO2 nucleation layers (D-ZrO2) were fabricated as follows: A 2-nm-thick bottom-ZrO2 layer was deposited on the BE-TiN by ALD at 300°C using (C5H5)Zr[N(CH3)2]3 precursor and H2O gas. Next, a 10-nm-thick HZO film was deposited on the bottom-ZrO2 layer by ALD at 300°C using (Hf/Zr)[N(C2H5)CH3]4 (Hf/Zr = 1/1) cocktail precursor and H2O gas. A 2-nm-thick top-ZrO2 layer was then deposited on the HZO film using the same ALD conditions. After that, post-deposition-annealing (PDA) was carried out at 600°C for 1 min in a N2 atmosphere. Finally, TE-TiN was fabricated on the top-ZrO2 layer by DC sputtering. Two types of TiN/HZO/TiN capacitors with 10-nm-thick HZO films were also prepared as references. One is the capacitor annealed before TE-TiN deposition (w/o), the other is the capacitor annealed after TE-TiN deposition under the same annealing process (D-TiN). The Hf:Zr ratio in the HZO film was estimated to be 0.43:0.57 by energy dispersive x-ray spectroscopy analysis. Fig. 1 shows the polarization-electric field (P-E) hysteresis curves of w/o, D-TiN, and D-ZrO2. All of the capacitors exhibited hysteresis loops in the range from −3.0 to 3.0 MV/cm. The 2P r value was increased in the following order: w/o (12 µC/cm2) < D-TiN (24 µC/cm2) < D-ZrO2 (29 µC/cm2). The ratio of ferroelectric orthorhombic phase was increased in the following order: w/o < D-TiN < D-ZrO2, from x-ray diffraction patterns (not shown). Therefore, we determined that the top- and bottom-ZrO2 nucleation layers play an important role for the ferroelectric orthorhombic phase formation of HZO films. Fig. 2 shows the relationship between the J value at 1.0 V and the 2P r value of w/o, D-TiN, and D-ZrO2. For D-TiN case, the 2P r value was approximately 2.0 times larger than that of w/o probably due to the mechanical stress from TE-TiN. However, the J value of D-TiN was increased in the low voltage region compared to w/o. On the other hand, for D-ZrO2 case, the 2P r value was about 2.4 times larger than that of w/o. Moreover, the J value of D-ZrO2 was lower by one order of magnitude than that of D-TiN due to the larger thickness of D-ZrO2 than that of D-TiN. Based on these experimental results, the HZO films exhibited significantly superior ferroelectricity using double ZrO2 nucleation layers compared to that fabricated using double TiN stressor layers. This work was supported partly by Grant-in-Aid for JSPS Research Fellow and CREST, JST. [1] J. Müller et al., Appl. Phys. Lett. 99, 112901 (2011). [2] S. J. Kim et al., Appl. Phys. Lett. 111, 242901 (2017). [3] T. Onaya et al., Appl. Phys. Express 10, 081501 (2017). Figure 1

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon–oxide–nitride–oxide–semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.

Highly sensitive and rapid MicroRNA detection for cardiovascular diseases with electrical double layer (EDL) gated AlGaN/GaN high electron mobility transistors

This study reports the development of an efficient and sensitive method to directly sense microRNA (miRNA) in high ionic strength solutions with the use of electrical double layer (EDL) gated AlGaN/GaN high electron mobility transistor (HEMT). This FET structure uses a complementary DNA probe functionalized gate electrode which is separated from the transistor channel. In this research, we focus on the detection of miRNA samples, miR-126, miR-208a and miR-21 which are biomarkers of cardiovascular diseases (CVD). The sensor has a dynamic range that is comparable to the clinically relevant concentration range with a detection limit as low as 1 fM. Selectivity of the sensor is demonstrated by evaluating sensor response at fully complementary and slightly mismatched sequences. The miniaturized sensor can be used in point of care or homecare diagnostics for rapid miRNA detection to evaluate CVDs at an early stage.

A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets

In this paper, we propose and simulate a new structure of a line tunnel FET employing gate over source-channel overlap pockets (GO-SCOPs). The SCOPs create vertical tunneling path within the source and the channel extension that lead to a faster thinning of the lateral tunneling barrier between the source and channel regions. As a result, an inverted C-shaped tunnel junction is formed providing both lateral tunneling and vertical tunneling. A calibrated 2-D simulation study shows that an ON-current improvement by one order is achieved in comparison with the gate over source only (GoSo) tunnel field-effect transistors with pockets. Further, the OFF-state leakage and average subthreshold swing are reduced by 44% and 21%, respectively, with an improved parasitic capacitance. This has improved the cutoff frequency from 8.3 MHz in GoSo with pockets structure to 1.19 GHz in the proposed GO-SCOP structure. Furthermore, by employing Ge SCOPs, the ON current is boosted by 4 orders of magnitude, maintaining leakage at ~0.25 fA/μm, giving ION/IOFF > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> , and a much improved average subthreshold swing of ~48 mV/dec at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 2 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V.

(Invited) Investigation of Critical Interfaces in Few-Layer MoS2 Field Effect Transistors with High-k Dielectrics

Transition metal dichalcogenides (TMDs) as 2D or few-layer semiconducting channel material are being widely studied to lower power consumption and obtain negligible short channel effects with continued transistor scaling [1-4]. Meanwhile, research needs to be conducted on top-gated, metal-oxide-semiconductor field effect transistors (MOSFETs) to correctly assess the possibility of TMDs supplanting silicon in the channel region. This is because top-gate device architectures face some key integration challenges that typical bottom-gate TMD FET structures do not experience. As an example, molybdenum disulfide (MoS2) is supposed to have no dangling interfacial bonds, making it difficult to form high-k dielectrics on them. Therefore, surface functionalization of TMDs has attracted attention [5-12]. However, detailed understanding on performance of transistors with metal/high-k/TMD top-gate stacks are still lacking. In addition, a major hurdle of incorporating these two-dimensional (2D) materials in device structures of any kind is the high contact resistance at the metal/TMD interface [13-15]. Recent results have shown that the backside dielectric can influence top-gate MOSFET performance [16]. In this work, few-layer MoS2 FET-based devices were fabricated using top and bottom high-k dielectrics (Al2O3 and/or HfO2). The C-V response of a top-gate, HfO2/MoS2 gate stack on a backside SiO2 layer demonstrated the existence of specific defects at the interface, which demonstrated frequency dependent “humps” in depletion – similar to conventional Si MOSFETs with unpassivated silicon dangling bonds in the dielectric/Si interfacial region. Also, a comparison of UHV and HV metal deposition on MoS2 as contacts for source and drain was done where results demonstrated that UHV deposited metals were superior to HV ones. In an additional experiment with Al2O3 as the bottom-gate dielectric layer, the intrinsic mobility and subthreshold slope were greatly improved compared to SiO2 or HfO2 as back gate dielectric FETs, indicating a positive influence on top-gate device performance even without any backside bias. Furthermore, a forming gas anneal is found to further enhance device performance due to a reduction in charge trap density at dielectric interfacial regions, and improved metal contact formation. Another significant finding in top-gate FET performance is the high-k dielectric screening effect of the backside Al2O3 layer. Results demonstrate that the extracted top-gate field effect mobility values are higher compared to SiO2 or HfO2 as a backside oxide – even though all FETs have the same top-side HfO2 dielectric oxide and no back bias. Acknowledgement – This work was supported in part by the US/Ireland R&D Partnership (UNITE) under the NSF award ECCS-1407765, Science Foundation Ireland under the US-Ireland R&D Partnership Programme Grant Number SFI/13/US/I2862, and the center for Low Energy Systems Technology (LEAST), one of six SRC STARnet Centers, sponsored by MARCO and DARPA.