Abstract
This article introduces a circuits model for a proposed spin-based device called a spin–orbit torque field-effect transistor (SOTFET) that can operate as a nonvolatile memory and logic device. The SOTFET utilizes an FET structure with a ferromagnetic-multiferroic (MF) gate-stack that enables read/compute and write functions to be isolated. This is achieved by a combination of a ferromagnetic layer that is programmable via spin–orbit torque coupled to an MF layer that also couples into the gate of a traditional FET. Additionally, this device has logic gate-like behavior and can be designed to operate in either AND or OR gate mode. We begin with a physics-based model of this device and derive a SPICE level model that can be integrated into the Cadence toolset. Using such a device we demonstrate MRAM, content addressable memories (CAM), and ternary CAM (TCAM) functionality with 3 to 5 transistors, a significant decrease over the CMOS alternative circuits, showing that such a device can enable low cost and compact associative memories not currently feasible with CMOS devices.
Highlights
F OR THE past decade, semiconductor device research has focused on finding ways to extend the scaling path of the semiconductor industry (i.e., Moore’s law) through the development of post-CMOS devices
The organization of the rest of this article is as follows: In Section II, we describe the device structure and principle of operation; in Section III, we describe our circuit-level compact model; in Section IV, we present the device as a logic device whose logic function depends on three major parameters; in Section V, we introduce RAM, content addressable memories (CAM), and ternary CAM (TCAM) topologies, which are verified using our compact model; Section VI discusses the results, points out some limitations and compares to both standard CMOS and field-effect transistors (FeFET) equivalent circuits; Section VII concludes
Successful spin– orbit torque field-effect transistor (SOTFET) operation will require achieving a hierarchy of energy couplings such that the magnetic exchange and Dzyaloshinskii–Moriya interaction (DMI) are stronger than the coercive forces that resist switching of P; an experimental group at Cornell is working toward this goal
Summary
F OR THE past decade, semiconductor device research has focused on finding ways to extend the scaling path of the semiconductor industry (i.e., Moore’s law) through the development of post-CMOS devices. Several memory devices, including ferroelectric field-effect transistors (FeFET) [1], resistive RAM (RRAM) [2], phase change RAM (PCRAM) [3], and magnetic-tunnel-junction-based RAM (MTJ-MRAM) [4] have been developed Of these technologies, FeFETs and two types of MTJ-MRAMs, switched by spin-transfer torque (STT-MRAM) or spin–orbit torque (SOT-MRAM), have shown promise in demonstrating nonvolatile, reliable and relatively low power performance, and have made the most progress toward commercialization. The proposed SOTFET, or SOT FET, as shown, will use SOT to write the magnetization of the ferromagnet (FM) and will read out the device state through a multiferroic (MF) (ferroelectric) FET gate-stack In this way, we expect to boost the on–off ratio to a value typical for an FET, on the order of or greater than 105. The organization of the rest of this article is as follows: In Section II, we describe the device structure and principle of operation; in Section III, we describe our circuit-level compact model; in Section IV, we present the device as a logic device whose logic function depends on three major parameters; in Section V, we introduce RAM, CAM, and TCAM topologies, which are verified using our compact model; Section VI discusses the results, points out some limitations and compares to both standard CMOS and FeFET equivalent circuits; Section VII concludes
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