FET Devices Research Articles

Antigen-Dissociation from Antibody-Modified Nanotransistor Sensor Arrays as a Direct Biomarker Detection Method in Unprocessed Biosamples.

The detection of biomolecules is critical for a wide spectrum of applications in life sciences and medical diagnosis. Nonetheless, biosamples are highly complex solutions, which contain an enormous variety of biomolecules, cells, and chemical species. Consequently, the intrinsic chemical complexity of biosamples results in a significant analytical background noise and poses an immense challenge to any analytical measurement, especially when applied without prior efficient separation and purification steps. Here, we demonstrate the application of antigen-dissociation regime, from antibody-modified Si-nanowire sensors, as a simple and effective direct sensing mechanism of biomarkers of interest in complex biosamples, such as serum and untreated blood, which does not require ex situ time-consuming biosample manipulation steps, such as centrifugation, filtering, preconcentration, and desalting, thus overcoming the detrimental Debye screening limitation of nanowire-based biosensors. We found that two key parameters control the capability to perform quantitative biomarkers analysis in biosamples: (i) the affinity strength (koff rate) of the antibody-antigen recognition pair, which dictates the time length of the high-affinity slow dissociation subregime, and (ii) the "flow rate" applied during the solution exchange dissociation step, which controls the time width of the low-affinity fast-dissociation subregime. Undoubtedly, this is the simplest and most convenient approach for the SiNW FET-based detection of antigens in complex untreated biosamples. The lack of ex situ biosample manipulation time-consuming processes enhances the portability of the sensing platform and reduces to minimum the required volume of tested sample, as it allows the direct detection of untreated biosamples (5-10 μL blood or serum), while readily reducing the detection cycle duration to less than 5 min, factors of great importance in near-future point-of-care medical applications. We believe this is the first ever reported demonstration on the real-time, direct label-free sensing of biomarkers from untreated blood samples, using SiNW-based FET devices, while not compromising the ultrasensitive sensing capabilities inherent to these devices.

Fabrication of Self-Assembly Metal /Semiconductor Heterostructured Nanowires By Using Anodic Aluminum Oxide (AAO)-Assisted Molding Injection Process

Self-assembly metal/semiconductor heterostructured Cu-Ge alloy nanowires were successfully synthesized by using the anodic aluminum oxide (AAO) template-assisted vacuum casting process for the first time, analyzed their interface microstructures and fabricated single nanowire into device. AAO, a membrane with a controllable microstructure of nano-channel array, was utilized to synthesize nanowires of the identical stoichiometry to bulk materials, combining with solid-liquid-solid transformation process. Through choosing a suitable hypoeutectic or hypereutectic composition ratio the size effect will force the phases of nanowires to solidify alternatively along axial direction. Thus, self-assembly nanowires with an alternative metal/semiconductor heterostructure can be obtained. Furthermore, a single nanowire device was synthesized to investigate the relative electrical properties for semiconductor applications. This results are useful in developing metal/semiconductor heterostructured nanowires for advanced FET devices. Figure 1

Favorable Combination of Schottky Barrier and Junctionless Properties in Field-Effect Transistors for High Temperature Applications

High-temperature transistors are of great interest for industrial applications, for instance, oil&gas and geothermal exploration, avionic, space, automotive and energy conversion. Especially, energy conversion electronics using wide-bandgap power transistors, i.e. SiCFET, in combination with high-temperature silicon gate-driver circuits can significantly increase system efficiency and reduce costs [1]. Our improved planar virtually dopant-free silicon-based double gate SOI FET with Ni and WTiN front-gate electrodes demonstrates ultra-low drain leakage currents at high-temperatures opening a path to record operating temperatures for silicon-based FET devices. Device Structure The long-channel device fabrication relies on a standard CMOS-compatible prototyping process using SOITEC Smart-Cut™ SOI-substrates with the lowest commercially available boron background doping of 1E15cm-3 enabling high carrier mobilities. Mid-gap Schottky barrier (SB) contacts are fabricated via nickel silicidation. The metal front-gate (FG) electrode consist of reactively sputtered WTiN for NMOS or Nickel for PMOS operation on a 8nm thick SiO2 gate dielectric. Channel height (CH) is approximated to 15nm. The back-gate (BG) formed by the silicon handle wafer is insulated by 145nm buried SiO2 (BOX) (Fig.1). Device Operation The device is modeled as a combination of two interacting FETs, one fully ambipolar Schottky barrier backside FET and a second unipolar junctionless (JL) topside FET [2,3]. The BG influences the whole body layer including the S/D Schottky barriers forming an ambipolar enhancement mode SBFET. Therefore, the dominant charge carrier type, i.e. electrons (VBG»0V) or holes (VBG«0V) in the channel region is defined by the BG polarity. In this configuration, the channel is located close to the body silicon to BOX interface (Fig.3). The charge carriers originate from the mid-gap NiSi SB contacts and enter the body layer at room temperature mainly by thermionic field emission (TFE) and at elevated temperatures by thermionic emission (TE) (Fig.2). In contrast, the depletion mode JLFET formed by the FG electrode only locally affects the charge carrier density in the middle of the channel and controls the current flow between source and drain with excellent electrostatic control as illustrated by the carrier density simulation in Fig.3. The combination of the enhancement and depletion mode operation in one device can appositely be summarized as enhancement suppression or dehancement mode operation (DeFET). Results & Discussion P- and NMOS transistor behavior is realized by applying the appropriate BG polarity to the very same device enabling transistor level reconfigurability (Fig.4). Maximum on-state current and threshold voltage are proportional to the magnitude of VBG (Fig.4). The work function difference between Ni and WTiN metal front-gate devices as well as process variations result in a significant threshold shift (Fig.4). The channel height (Fig.1) is a crucial parameter in device fabrication as it directly affects the off-state leakage current and threshold voltage [7]. Regarding high-temperature performance, the use of the SOI substrate eliminates bulk drain leakage while the introduction of SB contacts minimizes the band-to-band tunneling effect in comparison to classic steep S/D pn-junctions. For rising operating temperatures up to 470K, the on-state current increases from 8 to 46µA as TFE and TE increase allowing an overcompensation of the temperature dependent carrier mobility degradation effect (Fig.5,right). At the same time the drain leakage current is only increasing from <100fA to 2nA from 300 to 470K due to the high potential barrier induced by the FG (Fig.5,left). Gate leakage currents are <6pA during all measurements. Furthermore, PMOS behavior with nickel metal front-gate follows the same trends. Device simulations predict that reducing the channel height and introducing mid-κ gate dielectrics, i.e. Al2O3, renders record operating temperatures possible even for scaled devices limited only by reliability. Comparing the here presented DeFET generation with previous generations and other long-channel Si-based high-temperature FET structures illustrates the clear advantage of our device concept in suppressing drain leakage currents at high temperatures (Fig.6) [4-7]. Conclusion In this contribution, we demonstrate by means of experimental measurement data and device simulations the significantly improved drain leakage suppression at high operating temperatures of the planar dehancement mode FET CMOS technology in comparison to our previously published results in [7]. The combination of SB and JLFET properties opens a possible path for silicon based FET operation up to temperatures of 700K for various industrial applications.

A Simple Behavioral Electro-Thermal Model of GaN FETs for SPICE Circuit Simulation

This paper develops a behavioral electro-thermal model of GaN FETs for power-electronic circuit simulation in SPICE software environment. The model couples an available GaN FET electrical model with a thermal $RC$ network for junction temperature estimation, while using modification circuits between an eGaN FET device and its gate driver to embed thermal impacts on the device performance. Both the static and switching characteristics of the developed model are compared with those from the original electrical model. Performance and functionality of the developed electro-thermal model in a boost converter, based on time-domain simulation studies in the SPICE environment, are evaluated and experimentally verified.

Favorable Combination of Schottky Barrier and Junctionless Properties in Field-Effect Transistors for High Temperature Applications

High-temperature capable transistors are of great interest for industrial applications, for instance, oil & gas and geothermal exploration, avionic, space, automotive and energy conversion. Especially, energy conversion electronics using wide-bandgap power transistors, i.e. SiC- or GaN-based FET, in combination with high-temperature silicon gate-driver circuits can significantly increase system efficiency and reduce costs. Our improved planar virtually dopant-free silicon-based double gate SOI FET with reactively sputtered WTiNx front-gate electrodes demonstrates ultra-low drain leakage currents at high-temperatures opening a path to record operating temperatures for silicon-based FET devices.

Ultra‐Long Crystalline Red Phosphorus Nanowires from Amorphous Red Phosphorus Thin Films

AbstractHeating red phosphorus in sealed ampoules in the presence of a Sn/SnI4 catalyst mixture has provided bulk black phosphorus at much lower pressures than those required for allotropic conversion by anvil cells. Herein we report the growth of ultra‐long 1D red phosphorus nanowires (&gt;1 mm) selectively onto a wafer substrate from red phosphorus powder and a thin film of red phosphorus in the present of a Sn/SnI4 catalyst. Raman spectra and X‐ray diffraction characterization suggested the formation of crystalline red phosphorus nanowires. FET devices constructed with the red phosphorus nanowires displayed a typical I–V curve similar to that of black phosphorus and a similar mobility reaching 300 cm2 V−1 s with an Ion/Ioff ratio approaching 102. A significant response to infrared light was observed from the FET device.

Ultra-Long Crystalline Red Phosphorus Nanowires from Amorphous Red Phosphorus Thin Films.

Heating red phosphorus in sealed ampoules in the presence of a Sn/SnI4 catalyst mixture has provided bulk black phosphorus at much lower pressures than those required for allotropic conversion by anvil cells. Herein we report the growth of ultra-long 1D red phosphorus nanowires (>1 mm) selectively onto a wafer substrate from red phosphorus powder and a thin film of red phosphorus in the present of a Sn/SnI4 catalyst. Raman spectra and X-ray diffraction characterization suggested the formation of crystalline red phosphorus nanowires. FET devices constructed with the red phosphorus nanowires displayed a typical I-V curve similar to that of black phosphorus and a similar mobility reaching 300 cm(2) V(-1) s with an Ion /Ioff ratio approaching 10(2) . A significant response to infrared light was observed from the FET device.

Comparative analysis of adiabatic full adder cells in CNFET technology

The advent and widespread use of portable devices and their large market share have turned the spotlight on low-power design of such battery-operated systems. Arithmetic unit is the heart of a media processor embedded in portable electronic devices. Therefore, a low-power implementation of full adder cell, which is the basic building block of arithmetic structures, may significantly reduce the whole power of the mentioned systems. One of the well-known methods for reducing power dissipation in systems with high switching activity is the adiabatic logic. Due to the problems of the MOS scaling, carbon nanotube field effect transistor (CNFET) has been introduced as the most promising replacement for today’s FET devices. In this paper, various hybrid topologies of full adder cell are reviewed and implement based on the adiabatic logic with reduced transistor count. The simulations are conducted under various conditions such as different operating frequencies, load capacitors and supply voltages that may occur in realistic conditions. Moreover, ripple carry adder is realized in both adiabatic and non-adiabatic families in order to carry out more comprehensive analyses. Finally, regarding the fact that integrated circuits in Nano regime are much more sensitive to process variations, the robustness of such circuits against these variations is surveyed and analyzed.

(Invited) Vertical Nanowire FET Integration and Device Aspects

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

Thickness-dependent carrier transport and optically enhanced transconductance gain in III-VI multilayer InSe

Multilayer InSe with a thickness above ∼20 nm, is a direct semiconductor with a peak absorption wavelength approaching λ = 1000 nm, which is a promising candidate for solar-energy conversion and 2D optoelectronics devices. We present herein the experimental observations of thickness-dependent conductivity and photoconductive-responsivity spectrum in multilayer InSe as well as optically enhanced transconductance gain in the multilayer InSe metal-semiconductor-field-effect transistor (MESFET) illuminated by a halogen lamp. The voltage-current (V-I) measurement result shows multilayer InSe belongs to a p-type semiconductor, which can form a p-channel FET device. Thickness (t) dependent conductivity (σ) of multilayer InSe reveals about six-order variation from 5076 (Ω-cm)−1 (t = 5 nm) to 2.56 × 10−3 (Ω-cm)−1 (t = 184 μm, bulk) following a relationship of σ ∝ t−1.38. The highest conductivity in a thin InSe (e.g. t = 5 nm) is due to the increase of carrier density when the thickness is decreased. The photoresponsivity spectrum of a Ag-InSe-Ag multilayer photoconductor demonstrates a prominent peak absorption at 1.1 ∼ 1.3 eV, matches well with the direct-free-exciton energy of the InSe. A multilayer p-InSe MESFET was tested by V-I measurement. The transconductance was measured and determined to be The gm value will enhance about three times when the MESFET was placed under the illumination of a tungsten halogen lamp of a lower power density ∼0.5 mW · cm−2. All the experimental results demonstrate multilayer InSe a promising 2D material available for microelectronics and optoelectronics applications.

A Novel and Robust Packaging Technology for Miniaturized FET-Based Biosensors with Microfluidic Channels

FET devices are extensively used for sensors, including gas sensors and biosensors. In contrast to traditional resistive devices, FET has transconductance gain, which can significantly improve the S/N ratio. Recently, more applications in biosensors combine microfluidic channels and FET system. In FET-based biosensors, the wafer manufacturing process always requires a lot of cost, and it is used for metal lines as interconnects. Miniaturized chip plays a key role in reducing the manufacturing cost. However, simultaneously integrating the sensor and microfluidic channels on one chip is challenging. In this study, a novel and robust packaging method has been developed, to effectively reduce the size of the sensor chip and thereby the cost. 1 mm2 FET sensor chip has been fabricated and embedded in epoxy. Photolithography and metal deposition were done followed by lift-off process for metal interconnect. The FET-embedded chip was passivated and covered by the microfluidic channel made of PMMA.

Growth of High Material Quality Group III-Antimonide Semiconductor Nanowires by a Naturally Cooling Process.

We report on a simple but powerful approach to grow high material quality InSb and GaSb nanowires in a commonly used tube furnace setup. The approach employs a process of stable heating at a high temperature and then cooling down naturally to room temperature with the nanowire growth occurred effectively during the naturally cooling step. As-grown nanowires are analyzed using a scanning electron microscope and a transmission electron microscope equipped with an energy-dispersive X-ray spectroscopy setup. It is shown that the grown nanowires are several micrometers in lengths and are zincblende InSb and GaSb crystals. The FET devices are also fabricated with the grown nanowires and investigated. It is shown that the grown nanowires show good, desired electrical properties and should have potential applications in the future nanoelectronics and infrared optoelectronics.

A highly emissive distyrylthieno[3,2-b]thiophene based red luminescent organic single crystal: Aggregation induced emission, optical waveguide edge emission, and balanced ambipolar carrier transport

A highly emissive red luminescent single crystal which shows aggregation induced emission (AIE) property and optical waveguide edge emission based on small organic functional molecule, cyano-substituted 2,5-di((E)-styryl)thieno[3,2-b]thiophene (CNP2V2TT) has been prepared by the physical vapor transport (PVT) method. The fluorescence quantum efficiency of crystal is up to 37% and an emission peak maximum (λmax) locates at 645 nm. Cystallographic data indicate that uniaxially oriented molecular packing with slipped face-to-face π-π stacking forms by the hydrogen bonding network among CNP2V2TT molecules. The single crystal FET devices were fabricated using Au and Ca as hole and electron injection electrodes, respectively. The molecular design, introducing cyano groups into molecular skeleton, effectively lower the LUMO level and achieve well-balanced ambipolar electron (0.13 cm2 V−1 s−1) and hole (0.085 cm2 V−1 s−1) mobilities.

A Novel and Robust Packaging Technology for Miniaturized FET-Based Biosensors with Microfluidic Channels

FET devices are extensively used for sensors, including gas sensors and biosensors. In contrast to traditional resistive devices, FET has transconductance gain, which can significantly improve the S/N ratio. Recently, more and more applications in biosensors combine microfluidic channels and the FET system. In FET-based biosensors, the wafer manufacturing process always requires a lot of cost, and most of the chip area is used for metal lines as interconnect. Miniaturized chip plays a key role in reducing the manufacturing cost. However, simultaneously integrating the sensor chip and microfluidic channels on one chip is challenging. In this study, a novel and robust packaging method has been developed, to effectively reduce the size of the sensor chip and thereby the cost. 1 mm x 1 mm FET sensor chip has been fabricated and embedded in epoxy. Photolithography and metal deposition were done followed by lift-off process for metal interconnect. The FET-embedded chip was passivated and covered by the microfluidic channel made of PDMS. Figure 1 shows the schematic of the system and the final package size is 1cm x 1cm. Electrical measurement is also proceeded with liquid sample to confirm the usability. Figure 1

(Invited) Vertical Nanowire FET Integration and Device Aspects

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density. For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuits design. However, further cells scaling using conventional 2D layouts is becoming more and more challenged by key factors such as the physical limits on gate and contact placement and interconnect routing congestion. Vertical nanowire (VNW) devices appear particularly well placed to overcome some of these limitations, but require early process-design cross-disciplinary interactions to address the technological and design challenges/opportunities of moving from a 2D to a 3D layout configuration for CMOS. In this work, we will address some of these aspects, focusing first on a comparative analysis review of performance, parasitics and layout efficiency between VNWFETs (3D layout) and lateral nanowire (LNW) FETs or finFETs (2D layout), followed by a comprehensive overview of some key integration aspects regarding VNWFET devices fabrication. In VNWFETs, since the gate length (Lgate) is defined vertically, it can be relaxed without area penalty, which in turn also allows some relaxation in the NW diameter, while keeping optimum short-channel-effects control. This is an important advantage of the vertical device architecture as several theoretical studies predict mobility degradation below a certain NW dimension, which would also cancel off the gains of using high-mobility channels such as Ge or III-V over silicon [1,2]. Moreover, Lgate relaxation is an important knob for variability optimization and leakage control, critical in scaled SRAMs. In terms of layout, VNWFETs can enable more compact cells [2,3], for instance by placing two pull-up transistors on the same row of a SRAM cell, saving around 30% area in comparison to a finFET-based SRAM [2]. A comparative simulation analysis in [4] of NAND library cells also suggests promising speed gains and power consumption reduction when switching from a 7nm Si-baseline finFET technology to 5nm Si VNWFETs. In addition, despite their potential for lower parasitic RC, VNWFETs asymmetry for source/drain wiring needs to be taken into account in circuit design and in processing for bottom access resistance optimization [2,5]. From an integration perspective, two main routes can be considered for device fabrication: channel-first or channel-last. In this work, we will focus on the first approach for added flexibility in terms of channel material choice [Si, (Si)Ge, III-V] and also control of the channel (defects) quality. Channel body (NW pillar) definition is done using 193nm immersion lithography followed by dry-etch. For the particular case of III-V, a bottom-up approach can also be considered for the NWs growth [6] (Fig.1). NW diameter (CD) shrinkage by dry-etch is challenged by the local CD uniformity control of the pillars within the NW arrays and their high aspect-ratio. Further CD reduction, and potentially also smoothening of the NW sidewalls, can be obtained by applying n cycles of low-temperature, [O3-oxidation -> oxide etch] for Si-based pillars, digital etch for III-V pillars [7]. With regards to Si NW doping, for simplicity in terms of junction formation, we rely on growing up to three stacked layers of (uniformly doped) Si epi. A wide doping range for a given layer and a sharp doping concentration steepness between doped regions are feasible via tuning of the growth conditions such as pressure and B2H6 flow (for B-doped Si epi, PMOS). For extra simplicity, junctionless type of devices can also be particularly interesting to consider as they do not require junctions [8]. In a vertical device flow, control of the thickness of the different layers surrounding the NW pillars is key (Fig.2), both for a gate-first or a gate-last scheme, the latter enabling further options for device fabrication such as decoupling the gate module from doping/series resistance optimization for the top part of the NW. Here, layout dependences observed for several dry and wet etch processes and specific etch-back challenges (e.g., W surface roughness control) triggered the need for introduction of alternative schemes for improved process control of the layers on the wafers.

Improving FET Properties of Semiconducting Single-Walled Carbon Nanotubes by Selective Extraction

A semiconducting single-walled carbon nano-tube (s-SWNT) FET was prepared using the simple technique of selective extraction. The Raman spectrum of the transistor reveals that the metallic SWNTs and regioregular poly(3-dodecylthiophene) were completely removed, leaving only s-SWNTs. The drain current–drain voltage ( $I_{D}$ – $V_{\mathrm {DS}})$ characteristics of an SWNT FET device in the dark were measured. The transistor fabricated by our selective extraction exhibits a high ON/OFF ratio of $10^{7}$ and a subthreshold swing of 154 mV/decade. The effective s-SWNT sorting process herein can be applied to further devices in the future.

Thienoisoindigo-based small molecules and narrow bandgap polymers synthesized via C-H direct arylation coupling

Thienoisoindigo (TIIG) has emerged as an attractive building block for high-performance organic optoelectronic devices. Here we report the first synthesis of a series of π-conjugated TIIG-based small molecules and alternating copolymers via direct C–H arylation, which enables the efficient synthesis without use of flammable and toxic orgametallic reagents in fewer steps compared Suzuki and Stille coupling. The direct arylation coupling between TIIG and two respective mono-bromo aryl reactants clearly shows that the α-H is more reactive than the β-H in the thiophene unit of TIIG. The high regioselectivity of TIIG monomer warrants the successful synthesis of high-quality alternating copolymers with minimal structural defects. PTIIG-BT polymer synthesized via direct arylation polymerization (DAP) showed comparable molecular weight and hole mobility than the same polymer previously synthesized via Suzuki coupling. Moreover, the two new polymers (PTIIG-TF and PTIIG-2FBT) synthesized via DAP showed hole mobility up to 10−3 cm2 V−1 s−1 in FET devices fabricated and tested under ambient conditions. © 2016 Wiley Periodicals, Inc. J. Polym. Sci., Part A: Polym. Chem. 2016, 54, 2015–2031

Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate

In this work, we have developed a two-dimensional (2-D) analytical drain current model for cylindrical-gate tunnel FET structure with linearly graded binary metal alloy gate. The surface potential of the proposed model is determined using the solution of 2-D Poisson's equation with suitable boundary conditions. Further it paves way for the calculation of other analog parameters such as shortest tunneling distance, drain current, threshold voltage and subthreshold swing (SS). The introduction of linearly modulated work-function of binary alloy optimizes the subthreshold swing by ∼10 mV/decade as compared to conventional cylindrical-gate tunnel FET devices without degrading the drain current and threshold voltage performance. Also the present model shows the reduction in SS with down-scaling of gate oxide thickness and silicon pillar diameter. The analytical results are found to be synonymous with the results of Synopsys TCAD device simulator.

GaN FET単相PWMインバータによる高キャリア周波数励磁時の鉄損特性

The Iron loss at higher carrier frequencies up to 190kHz is measured by a single-phase GaN FET inverter because sinusoidal-like waveform is expected to be obtained by new material devices such as those based on SiC or GaN. The measured data show that iron loss excited by PWM inverter does not converge to the iron loss by sinusoidal excitation because the fluctuation in the magnetic field does not converge to zero, even when carrier frequency is 190kHz. Moreover, the iron loss even increases at some carrier frequency for a long dead time. Because of the properties of the GaN FET device, the ON voltage of the GaN FET during the dead time period becomes large, and the minor loop shape in the magnetic hysteresis curve becomes large. These phenomena are observed for a constant applied DC voltage and also for a constant modulation factor constant condition. The properties of the power semiconductor and the dead time of the inverter seriously influence the increase in the iron loss.

Design and synthesis of extended quinoxaline derivatives and their charge transport properties

A scalable and convenient strategy is described to synthesize extended conjugation quinoxaline derivatives from phenylene-ethynylene arrays. The fabricated FET devices possess good performance, with mobilities of 0.47 cm2 V−1 s−1 and 0.99 cm2 V−1 s−1.