FET Devices Research Articles

A Readout Channel Optimized for Minimum NEP of a FET-Based THz Pixel

This paper presents a high-gain, noise-efficient readout interface for a FET-based direct THz detector fabricated in 0.15 μm standard CMOS technology. The pixel, conceived to be used in array configuration for an imaging application, consists of an on-chip antenna, a FET device for THz signal detection and a chopper-stabilized readout interface performing in-pixel filtering and amplification. The switched-capacitor multistage design achieves a closed-loop gain of 70 dB and a system bandwidth of 1 kHz, thereby improving the SNR and limiting the total integrated input referred noise of the channel to less than the minimum detectable signal limit defined by the FET detector. The measurement results show that the pixel is able to achieve a maximum voltage responsivity of 470 kV/W and a minimum NEP value of 480 pW/√Hz at the antenna frequency of 370 GHz. The pixel consumes 200 μW power, and it occupies an area of 0.375mm2.

(Invited) Scalable, Layer-Controlled Synthesis of 2D Semiconductors

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, transition metal dichalcogenides (TMDs) with a unique layered structure have attracted tremendous interest in recent years mainly motivated by the characteristic 2D nature together with distinctive and tunable optoelectronic properties which make them appealing for a wide variety of applications. Their ultra-thin body nature, in particular, is expected to provide superior immunity to short channel effects therefore extending the potential to scale transistors down to the few-nanometer-scale. [1-4] Another key feature of 2D materials is the absence of surface dangling bonds. The latter property has the potential to eliminate lattice mismatch constraints thus paving the way for hybrid integration of TMDs into artificial heterostructures with sharp interfaces and designed band alignment. As researchers explore the physics and applications of layered semiconductors, it is now becoming important to find a wafer-scale path towards technology implementation and integration of these novel materials. In this context, it has been recently demonstrated that metal-organic chemical vapor deposition (MOCVD) can be used to manufacture large area 2D semiconductor materials. [5]. The goal of this work is to unravel some of the fundamental aspects of film formation and provide a pathway towards a layer-controlled, wafer-scale synthesis of TMD films. More in details, we will provide insights on the different growth mechanisms of TMD films on amorphous and crystalline templates. In this framework, we will discuss the key aspects to enable and control a real van der Waals epitaxy of TMD films. The target, of course, is to achieve unidirectional and high quality monocrystalline domains by forcing an epitaxial relationship between the 2D film and the underlying substrate. In-depth structural AFM, XPS, TEM analyses along with Raman, Photoluminescence and lifetime measurements are used in our study. In order to establish a direct link between electrical performance and material quality, FET devices using our layers are also fabricated. A careful link between the structural analyses and the electrical results is made in order to asses material quality and offer a step further on the understanding of 2D TMDs for nanoelectronics. B. Radisavljevic et al. Nature Nanotechnol., 6, 147 (2011).R. Ganatra and Q. Zhang, ACS Nano, 8, 4074 (2014).A. Nourbakhsh et al. Nano Lett., 16 7798 (2016).A. Nourbakhsh et al. Nanoscale, 18, 6122 (2017).K. Kang et al. Nature volume 520, 656 (2015)

Nanomechanical Properties of ALD Hafnium Oxide (HfO2) on Silicon-on-Insulator (SOI) and Strained Silicon-on-Insulator (sSOI) Films

Hafnium oxide is used as replacement for silicon oxide as a gate insulator in field-effect transistors [1]. HfO2 is used as a high-κ dielectric in DRAM capacitors and in advanced metal-oxide-semiconductor FET devices and in optical coatings [2]. Thin films of hafnium oxide (HfO2) were deposited by atomic layer deposition (ALD) on silicon-on-insulator (SOI) and benchmarked against strained-silicon-on-insulator (sSOI). Both types of films have been tested for surface morphology, crystal structure and nanomechanical properties. The nanomechanical properties have been tested using a nanoindenter from Keysight equipped with a three sided Berkovich diamond tip. The crystalline structure has been verified using X-ray diffraction. The surface morphology has been examined using atomic force microscopy (AFM) and the film thickness was verified using field emission scanning electron microscopy (FE-SEM) as indicated by the cross-sectional FE-SEM image as shown in Figure 1. We will discuss the structural and mechanical properties of the films citing the superiority of the ALD technique that is particularly used in the fabrication of the films that are presented in this study. References Intel (11 November 2007). "Intel's Fundamental Advance in Transistor Design Extends Moore's Law, Computing Performance".Zhu, C. Tang, L. R. C. Fonseca, and R. Ramprasad 47, 7399 (2012). Figure 1

(Keynote) Contemporary and Future Logic Devices

Headwinds faced by scaling efforts of high performance logic technology have forced engineering teams to go beyond dumb shrinking of device dimensions and into clever employment of new materials and structures, over last few technology nodes. We departed technology staple, planar transistors, and entered into 3D structures, half a dozen years ago. Such paradigm shifts will continue to happen more often in the years to come. We will look at today's state-of-the-art devices - FinFETs - and explore capability and suitability of new architectures for years to come. Those include variants of gate-all-around (GAA) transistors, horizontal and vertical, negative-capacitance FET (NCFET), tunnel FET (TFET), and spin-based devices. We'll assess feasibility of material contenders for better channel transport - III-V, SiGe/Ge, carbon nanotubes (CNT) and 2D transition metal di-chalcogenides (TMD). Finally, we discuss 3D monolithic device stacking and standard cell level design-technology co-optimization role in scaling.

(Invited) Degradable Conjugated Polymer with Exceptional Selectivity for Large Diameter Semiconducting Carbon Nanotubes

Separation of electronically pure, narrow dispersed, pristine semiconducting single walled carbon nanotubes (S-CNT) from a heterogeneous as-synthesized mixture is essential for various semiconducting technologies and biomedical applications. While conjugated polymers are essential for this sorting step, it is highly desirable to remove any organic residues from the resulting devices. We report here the design and synthesis of a mild acid degradable π-conjugated polyimine polymer (PFO-N-BPy) that is structurally analogous to the commonly used and commercially available poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-(6,6’-(2,2’-bipyridine))] (PFO-BPy). An acid cleavable imine link (-HC=N-) was introduced in the PFO-N-BPy backbone to impart degradability, which is absent in PFO-BPy. PFO-N-BPy was synthesized via a metal catalyst free Aza-Wittig reaction in high yields. PFO-N-BPy with a degree of polymerization of just ~10 showed excellent (> 99% electronic purity) selectivity for both large diameter (1.3-1.7 nm) arc-discharge S-CNTs and smaller diameter (0.8-1.2 nm) HiPCO S-CNTs. Overall, selectivity for semiconducting species is similar to that of PFO-BPy but with an advantage of complete depolymerization under mild acidic conditions into recyclable monomers. We further show by UV-Vis, X-ray photoelectron spectroscopy (XPS), and SEM that the PFO-N-BPy wrapped S-CNTs can be aligned into a monolayer array on gate dielectrics using a floating evaporative self-assembly process from which the polymer can be completely removed. Short channel FETs were fabricated from the polymer-stripped aligned S-CNT arrays which further confirmed the semiconducting purity on the order of 99.9% or higher. We will present the recent optimized FET device results using this removable polymer.

Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)

Tunnel field-effect transistors have shown great potential given their good scalability and low leakage current. However, they are associated with some drawbacks, including ambipolar behavior and low ON-state current relative to the MOSFET. To overcome these problems, a novel junctionless gate-all-around TFET (JL GAA TFET) is proposed. The proposed device employs a two-dimensional model by solving Poisson’s equation in 2D. The results are verified with the assistance of Sentaurus Device simulation software. The electrical and electrostatic characteristics of the JL GAA TFET, including its surface potential, energy band, electric field, threshold voltage and drain current, are studied using models and simulations. The impact of various gate insulator materials is also studied using the model, and the transfer current of the JL GAA TFET is compared with that of a different type of FET device. The JL GAA TFET exhibits a high $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio ( $$\sim 10^{9}$$ ) and a subthreshold slope of 28 mV/decade at room temperature for the high-kdielectric gate insulator material $$(\hbox {TiO}_{2})$$ . With regard to the use of the device in switching applications, the JL GAA TFET appears to be a good candidate.

Microspacing In-Air Sublimation Growth of Organic Crystals

Organic single crystals manifest the intrinsic physical properties of materials. However, traditional growth of organic single crystals is limited by low solubility from solutions or complexity from physical vapor deposition. Here we report a new method to grow organic single crystals by microspacing in-air sublimation, which avoids costly vacuum system and time-consuming procedures and is practical for a wide range of organic crystals. In situ crystal growth observation revealed an unprecedented vapor-to-melt-to-crystal mechanism, resulting from the micrometer scale spacing distance between the source and the growth position. FET devices based on the rubrene crystals directly grown on Si/SiO2 substrate exhibited higher mobility than the best record using SiO2 as the gate dielectric. This effective organic crystal growth technique can be affordable and handled for almost every lab, which may be beneficial for future research and application of organic crystals.

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.

Multicolor Spectral-Specific Silicon Nanodetectors based on Molecularly Embedded Nanowires.

Silicon-based photodetectors cannot distinguish between different wavelengths. Therefore, these detectors relay on color-specific filters to achieve color separation. Color filters add complexity to color sensitive device fabrication, and hinder miniaturization of such devices. Here, we report an ultrasmall (as small as ∼20 nm by 300 nm), red-green-blue-violet (RGBV) filter-free spectrally gated field effect transistor (SGFET) detectors. These photodetectors are based on organic-silicon nanowire hybrid FET devices, capable of detecting specific visible wavelength spectrum with full width at half-maxima (fwhm) under 100 nm. Each SGFET is controlled by a distinctive RGBV spectral range, according to its specific organic fluorophore functionalization. The spectral-specific RGBV detection is accomplished via covalent attachment of different fluorophores. The fluorophore molecules inject electrons into the nanowire structure as a result of light absorption at the appropriate RGBV spectral range. These photoinduced electrons modify the occupancies of the oxide's surface states, shifting the device threshold voltage, thus changing its conductivity, and functioning as a negative stress bias in a p-type SiNW FETs. A positive biasing can be achieved via UV light-induced ionization, which leads to detrapping and translocation of electrons at the oxide layer. Furthermore, a novel theoretical model on the mechanism of action of these devices was developed. Also, we show that suspended SGFETs can function as nonvolatile memory elements, which unlike fast-relaxing on-surface SGFETs, can store discrete "on" (RGBV illumination) and "off" (UV illumination) states for several days at ambient conditions. We also demonstrate a unique single-nanowire multicolor photodetector, enabling in principle a broad spectral detection over a single silicon nanowire element. These highly compact, spectral-controlled nanodevices have the potential to serve in various future novel optoelectric applications.

Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits

We analyze the performance of hybrid single-electron transistor (SET)–FET circuits when different variability sources are considered, e.g., SET’s quantum dot location and FET device dimension variations. For the FET device, FinFET and vertical nanowire configurations have been studied. The hybrid SET–FET circuits with both SET and FET in vertical topology depict the best circuit performance and the highest integration level. The variability impact on different SET-based circuits has been analyzed, including negative differential resistance and logic inverters.

Peptide aptamer-modified single-walled carbon nanotube-based transistors for high-performance biosensors

Biosensors employing single-walled carbon nanotube field-effect transistors (SWCNT FETs) offer ultimate sensitivity. However, besides the sensitivity, a high selectivity is critically important to distinguish the true signal from interference signals in a non-controlled environment. This work presents the first demonstration of the successful integration of a novel peptide aptamer with a liquid-gated SWCNT FET to achieve highly sensitive and specific detection of Cathepsin E (CatE), a useful prognostic biomarker for cancer diagnosis. Novel peptide aptamers that specifically recognize CatE are engineered by systemic in vitro evolution. The SWCNTs were firstly grown using the thermal chemical vapor deposition (CVD) method and then were employed as a channel to fabricate a SWCNT FET device. Next, the SWCNTs were functionalized by noncovalent immobilization of the peptide aptamer using 1-pyrenebutanoic acid succinimidyl ester (PBASE) linker. The resulting FET sensors exhibited a high selectivity (no response to bovine serum albumin and cathepsin K) and label-free detection of CatE at unprecedentedly low concentrations in both phosphate-buffered saline (2.3 pM) and human serum (0.23 nM). Our results highlight the use of peptide aptamer-modified SWCNT FET sensors as a promising platform for near-patient testing and point-of-care testing applications.

Analysis and Comparison of Intrinsic Characteristics for Single and Multi-channel Nanoplate Vertical FET Devices

In this paper, intrinsic characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were investigated for single and multichannel structure through 3-D technology computeraided design (TCAD) simulations. The vertical device has strong immunity for the unprecedented short channel effects (SCE) and intrinsic gate delay compared with the lateral device owing to the flexible expansion channel in vertical direction. The proposed single and multi-channel NP VFETs (NP height = 40 nm) exhibit excellent characteristics with ISUBon/SUB/ISUBoff/SUB 105, subthreshold swing (SS) 73 mV/decade, and draininduced barrier lowering (DIBL) 60 mV/V.

Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability

In this work, work-function variation (WFV) on 5 nm node gate-all-around (GAA) silicon 3D stacked nanowire FET (NWFET) and FinFET devices are studied for 6-T SRAM cells through 3D technology computer-aided design (TCAD) simulation. The NWFET devices have strong immunity for the unprecedented short channel effects (SCEs) compared with the FinFET devices owing to increased gate controllability. However, due to the narrow gate area, the single NWFET is more vulnerable to WFV effects than FinFET devices. Our results show that the WFV effects on single NWFETs are larger than the FinFETs by 45–55%. In the case of standard SRAM bit cells (high density: 111 bit cell), the variation of read stability (read static noise margin) on single NWFETs are larger than the FinFETs by 65–75%. Therefore, to improve the performance and having immunity to WFV effects, it is important to analyze the degree of variability in 3D stacked device architectures without area penalty. Moreover, we investigated the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of 3D stacked NWFET in 6-T SRAM bit cells.

Investigation of Work Function Variation Induced by Metal Gate and Process Variation Effect in 3D Stacked Nanowire FET Devices

Investigation of Work Function Variation Induced by Metal Gate and Process Variation Effect in 3D Stacked Nanowire FET Devices

(Invited) Critical Recent Advancement of GaN Technology and MMICs for Millimeter-Wave Applications

In this paper, we will present the in-development of Qorvo’s 90nm GaN technology imbedded within Qorvo’s existing 3-Metal-Interconnect (3MI) MMIC process flow, to make active and passive devices fully compatible with state-of-the-art GaN MMIC process, for V- and W-band MMIC High Power Amplifier (HPA) applications. By applying an advanced epitaxial material structure, dedicated T-gate configuration and process refinement, as well as 50-mm SiC substrate with Individual Source Via (ISV) FET construction, this technology demonstrates GaN FET devices with >145GHz Ft and >850mS/mm Gm, enables circuit designers to utilize this technology to pursue millimeter-wave market opportunities. Using this technology, a Technology characterization vehicle (TCV) MMICs using 5-stage 85GHz GaN power amplifiers have been demonstrated through circuit design, fabrication and measurements. This MMIC achieves greater than 38 dB small signal gain at 85GHz (8dB small signal gain per stage), and greater than 30 dB small signal gain over 72 – 90 GHz bandwidth. Further test results for both FET device and MMIC, including DC, small signal and power characteristics, will be reported in conference. This emerging GaN on SiC transistor technology is well suited for next generation millimeter-wave HPA, wideband and multi-function MMIC applications and beyond. This work was funded by ONR (Program Manager: Dr. Paul A. Maki, ONR N00014-13-C-0071). Figure 1

(Invited) Impact of Gate Dielectrics on the Threshold Voltage in MoS2 Transistors

Introduction MoS2 is a next-generation 2D material which is considered for applications in digital electronics [1–3]. Although enormous progress has been made in the area of MoS2 FETs, the available prototypes do not yet meet the high expectations. Commonly known reliability issues like the frequently observed hysteresis in the ID(VG) characteristics [4–6] and the large drifts of the threshold voltage over time [7] prohibit stable device operation for this technology. Apart from fabrication related issues, these performance limiting issues are the most critical obstacles inhibiting industrial applications of MoS2 FETs. Complementing our previous works [7–9], here we present a physical modeling approach for studying the charging and discharging of preexisting defects in the surrounding dielectrics. Devices We compare the hysteresis widths measured at the gates of MoS2 based FET devices at different sweep frequencies. Additionally, we study the drifts of the threshold voltage on these devices in a systematic way by evaluating the threshold voltage shifts observed after stressing the devices for different time spans and stress voltages. From the wide range of samples available, we choose devices using a thermal SiO2 layer as a back-gate dielectric. The MoS2 is either exposed to the ambient or covered by an amorphous Al2O3 layer. This thin dielectric layer enables a top gate contact and is at the same time necessary to prevent any degradation of the device characteristics due to the impact of the ambient [4,8]. Degradation Modeling For simulating the transfer characteristics we use a TCAD device simulator solving the drift-diffusion equations [10]. This approach is valid for devices with large dimensions and a large number of scattering centers, even if 2D channel materials are used [11]. The impact of interface defects is considered by using the standard SRH model. The transient charging and discharging of oxide defects leading to the hysteresis and the long-term drifts of the threshold voltage are described using the four-state NMP model [12,13]. The physical defect properties determining the degradation, such as trap positions and energy levels, depend on the respective oxide and have been studied in detail for SiO2 [8,14] and Al2O3 [9]. Results In accordance with our previous experimental work [7], we argue here that the common cause for the hysteresis in the ID(VG) and the observed long-term drifts are charge capture and emission events in the surrounding dielectrics. Even though several groups claim that the hysteresis is due to charge trapping at the interface [6,15,16], we argue here that interface traps can only impact the threshold voltage via a change in the sub-threshold slope. An observed hysteresis provides information about fast-switching oxide traps, while the systematic stress measurements reveal details about slow-switching oxide traps. One important quantity, necessary for understanding the size of the observed threshold voltage shifts, is the band alignment of the defect bands in the dielectrics with respect to the band edges of the semiconductors, illustrated in Fig. 1. Conclusions We use a drift-diffusion based simulation methodology to describe the cause of the threshold voltage drifts observed in the ID(VG) characteristics of MoS2 FETs, namely the charge capture and emission processes in the gate oxide traps. Thus, it is of utmost importance not only to investigate the fabrication of 2D layers, but also to focus on the quality and the defect bands of amorphous dielectrics to enable further progress in the area of FETs based on 2D materials. Acknowledgments The authors gratefully acknowledge financial support through FWF grant noI2606-N30.

Fabrication and Operation of Monolayer Mott FET at Room Temperature

Abstract Self-assembled monolayer FET based on a TTF derivative is described (FET = field-effect-transistor, TTF = tetrathiafulvalene). The molecule is anchored on an alumina dielectric layer through covalent bonding of a phosphonic acid linker. A p-type monolayer FET device is achieved and subsequent chemical doping of this monolayer with F4TCNQ dopants results in an ambipolar device. (F4TCNQ = 2,3,5,6-Tetrafluoro-7,7,8,8-tetracyanoquinodimethane) Several strange behaviors including a gate voltage shift upon doping seem to be consistent with organic monolayer Mott FET. Finally, temperature dependence of the FET performance, which also fit the anticipated Mott FET behavior, is discussed.

First Principles Study of Molybdenum Disulfide Electronic Structure

The study of two dimensional material has gain interest due to unique properties which are different from the bulk precursors. Mono- and few-layered of Transition metal dichalcogenides (TMDCs) has band gap properties between 1-2 eV that suitable of FET devices or any optoelectronic devices. Among TMDCs, Molybdenum Disulfide (MoS2) has gain interest due to its promising band gap-tuning and transition between direct to indirect band gap properties depends on its thickness. First principles calculation by Density Functional Theory has been performed to study the characteristic of MoS2 electronic structure. Indirect band gap of MoS2 lies between point Γ to Γ-K in first brillouine zone, while the direct bandgap lies in point-K. The indirect band gap became larger while the number of layer decreased due to quantum confinement effect in c axis direction. In monolayer MoS2, the indirect band gap become larger than direct one, band gap properties transitioned from indirect to direct. The unique bandgap properties of MoS2 can lead into better application in energy devices such as solar cell [11], FET [10], and photoluminescence device.

An Energy-Efficient Tensile-Strained Ge/InGaAs TFET 7T SRAM Cell Architecture for Ultralow-Voltage Applications

In this paper, we benchmark the read/write performance and standby power of several static random access memory (SRAM) cell architectures utilizing 45-nm Si CMOS MOSFET and/or tensile-strainedGe/InGaAs tunnel FET (TFET) devices under low-voltage operation ( $0.2~\text {V} \le \vert {V}_{\text {DD}}\vert \le 0.6$ V). We then introduce a novel tensile-strained Ge/InGaAs TFET-based SRAM circuit using several access schemes and investigate the impact of cell access design on static and dynamic performance. SRAM cells utilizing outwardaccess transistors exhibit wide read andwrite static noise margins, but suffer from increased read delay times. A 7T SRAM cell architecture is proposed in order to resolve the degraded read delay time. Cell standby energy was found to exhibit a strong dependenceon operational voltage andGe strain state. Variation of theGe strain state from 1.5% to 3% resulted in an up to 98% reduction in cell standby energy ( $\vert {V}_{\text {DD}}\vert = 0.6$ V) as compared with similar CMOS-based SRAM cells. These results demonstrate the superior performance of the proposed 7T TFET SRAM design for operation in the low- and ultralow-voltage regime.

(Invited) Electrical Atomic Force Microscopy for 2D Transition Metal Dichalcogenide Materials

As Si-based electronic devices are approaching their projected scaling limits, layered two-dimensional (2D) materials such as transition metal dichalcogenides (TMDs) are extensively studied as potential new channel materials and fundamental building blocks of emerging sensors and devices.[1-2] In this context, MoS2, WS2 and WSe2 to name a few, are now available for deposition trough different top down approaches. However, their outstanding properties are often degraded during the fabrication processes required for the device integration. For example, the selective growth of 2D TMDs their patterning and the electronics properties fine tuning still remain elusive. Here we report on electrical atomic force microcopy (AFM) and beam analysis techniques which are used to develop a framework of analysis for 2D materials. The latter is applied to understand the local properties of MoS2 comparing pristine material and structures which are selectively grown and patterned.[3] Different growth techniques are investigated. After modelling the tip-sample contact system, we assess the impact of the plasma-induced damages combining the electrical AFMs and Auger emission spectroscopy. We study the local electrical properties of grain boundaries and their transport respectively in pristine and patterned structures for FET devices by conductive atomic force microscopy (C-AFM). [1] G. Fiori, F. Bonaccorso, G. Iannaccone, T. Palacios, D. Neumaier, A. Seabaugh, S. K. Banerjee, and L. Colombo, “Electronics based on two-dimensional materials,” Nat. Nanotechnol., vol. 9, no. 10, pp. 768–779, 2014.[2] Desai, S. B., Madhvapathy, S. R., Sachid, A. B., Llinas, J. P., Wang, Q., Ahn, G. H., Javey, A. (2016). MoS 2 transistors with 1-nanometer gate lengths, 354(6308), 2–6.[3] Chiappe, D., Asselberghs, I., Sutar, S., Iacovo, S., Afanas’Ev, V., Stesmans, A., … Thean, A. (2016). Controlled Sulfurization Process for the Synthesis of Large Area MoS2 Films and MoS2/WS2 Heterostructures. Advanced Materials Interfaces, 3(4), 1–10.