A Readout Channel Optimized for Minimum NEP of a FET-Based THz Pixel

Abstract

This paper presents a high-gain, noise-efficient readout interface for a FET-based direct THz detector fabricated in 0.15 μm standard CMOS technology. The pixel, conceived to be used in array configuration for an imaging application, consists of an on-chip antenna, a FET device for THz signal detection and a chopper-stabilized readout interface performing in-pixel filtering and amplification. The switched-capacitor multistage design achieves a closed-loop gain of 70 dB and a system bandwidth of 1 kHz, thereby improving the SNR and limiting the total integrated input referred noise of the channel to less than the minimum detectable signal limit defined by the FET detector. The measurement results show that the pixel is able to achieve a maximum voltage responsivity of 470 kV/W and a minimum NEP value of 480 pW/√Hz at the antenna frequency of 370 GHz. The pixel consumes 200 μW power, and it occupies an area of 0.375mm2.