Thickness Of Ferroelectric Layer Research Articles

Temperature analysis of lead zirconate titanate GAA-NCFET nanowire with interface trap charges

This article explores the static and trap analysis of lead zirconate titanate negative capacitance gate-all-around (PZT NC GAAFET) nanowire at different temperature using Sentaurus 3D TCAD simulations. Impact of uniform and non-uniform trap charges on various electrical parameters for different ferroelectric (FE) layer thickness is investigated. Work delves the effect of interface traps, at Silicon-HfO2 interface, on electrical parameters of PZT NC GAAFET. Device yields subthreshold slope of 49 mV/dec, at TFE 20 nm, which surpasses Boltzmann tyranny limit. ION, IOFF, ION/IOFF, VTH, SS, and gm have enhanced owing to incorporation of PZT FE layer in contrast to baseline GAAFET. IDS-VGS of NC GAAFET evinces a positive (negative) shift for negative (positive) traps, owing to negative capacitance, compared to baseline for which it exhibits reverse shift. Moreover, the influence of interface trap charges, for NC GAAFET, prevails in subthreshold regime. Electrical parameters primarily deteriorate in presence of interface traps as temperature elevates.

Competing Charge Transfer and Screening Effects in Two-Dimensional Ferroelectric Capacitors.

Two-dimensional (2D) ferroelectrics promise ultrathin flexible nanoelectronics, typically utilizing a metal-ferroelectric-metal sandwich structure. Electrodes can either contribute free carriers to screen the depolarization field, enhancing nanoscale ferroelectricity, or induce charge doping, disrupting the long-range crystalline order. We explore electrodes' dual roles in 2D ferroelectric capacitors, supported by first-principles calculations covering a range of electrode work functions. Our results reveal volcano-type relationships between ferroelectric-electrode binding affinity and work function, which are further unified by a quadratic scaling between the binding energy and the transferred interfacial charge. At the monolayer limit, charge transfer dictates the ferroelectric stability and switching properties. This general characteristic is confirmed in various 2D ferroelectrics including α-In2Se3, CuInP2S6, and SnTe. As the ferroelectric layer's thickness increases, the capacitor stability evolves from a charge-transfer-dominated state to a screening-dominated state. The delicate interplay between these two effects has important implications for 2D ferroelectric capacitor applications.

Gradient voltage amplification effect in FDSOI NCFET with thickness-variable ferroelectric layer

In this paper, a negative capacitance field effect transistor with thickness variable ferroelectric layer (TVFL NCFET) based on the fully depleted silicon on insulator (FDSOI) is proposed. The TVFL NCFET features the linearly increased ferroelectric layer thickness along the channel from source to drain. The gradient voltage amplification effect caused by the TVFL is analyzed according to the proposed capacitance model and simulation. Both of the model and numerical results indicate that the TVFL leads to a gradient increased electrostatic potential distribution along the bottom of the ferroelectric layer. The influences of gradient voltage amplification effect on the transfer characteristics, the output characteristic, the ratio between on-state-current (I ON) and off-state-current (I OFF), the drain induced barrier lowering (DIBL) and the subthreshold swing (SS) are investigated. The results show that the TVFL NCFET achieves the SS of 53.14 mV/dec, which is reduced by 19% when compared to the conventional NCFET. Meanwhile, large ION/IOFF is also realized and up to 1012 at most.

Improvement of ferroelectric and dielectric properties in BaTiO3/LaNiO3 superlattices by regulating the ferroelectric layer thickness

Ferroelectric superlattices exhibit rich functional characteristics. Yet, the ferroelectric properties are always unsatisfactory due to the presence of depolarization field resulting from the polarization discontinuities between the component materials, which has become a bottleneck problem hindering the improvement of ferroelectric properties and further industrial applications. Here, the BTO/LNO superlattices composed of ferroelectric (BaTiO3, BTO) and metallic (LaNiO3, LNO) materials were prepared by pulsed laser deposition (PLD). The periodic thickness of the LNO layers was fixed to 2 unit cells, while the periodic thickness of the BTO layers was changed. We demonstrate experimentally that by regulating the BTO periodic thickness, BTO/LNO superlattices exhibit excellent and adjustable ferroelectric and dielectric properties. The enhancement of electrical properties is closely related to the increase of tetragonality (c/a) combined with the effect of the ultra-thin LNO layers and the accumulation of oxygen vacancies at superlattice interfaces on reducing the depolarization field. We hope this work will provide an effective strategy for optimizing the ferroelectric properties of ferroelectric superlattices based on the component material and periodic structure regulation.

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a negative capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40 nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, T fe of 3 nm, the energy consumption of the proposed accurate NCFET based CiM design is ∼82.48% lower in comparison to the conventional/Non CiM full adder design and ∼85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at V DD = 0.5 V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ∼4.19x lower energy consumption and ∼4.47x lower energy consumption in approximation mode when compared to the baseline 40 nm CMOS design at V DD = 0.5 V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

The physical origin of inhomogeneous field within HfO2-based ferroelectric capacitor

In this work, the origins of the inhomogeneous field within the HfO2-based ferroelectric (FE) capacitor are investigated. We propose a model to simulate the relationship between the reversed polarization and the applied pulses with different amplitudes and durations. The electric field distribution is considered to be influenced by the ferroelectric layer thickness (tFE) and the built-in field (Eb). Then, the distribution parameters of both two physical factors and the Merz law, which define the switching dynamics, could be obtained by fitting the experimental results. Comparing with the results of high-resolution transmission electron microscope and first-order reversal curve measurements, it can be reasonably concluded that the physical origin of the inhomogeneous field in HfO2-based ferroelectrics is the random distribution of tFE and Eb. This work improves the understanding of the switching dynamics by providing the origins of the inhomogeneous field in an FE film.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

This work demonstrates the reliability-aware analysis of the Junctionless negative capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e. 300 K). The device variation, i.e. Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc, on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor’s reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e. end of a lifetime. At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed junctionless negative capacitance FinFET-based H2 gas sensor.

Texture in atomic layer deposited Hf0.5Zr0.5O2 ferroelectric thin films

HfO2-based ferroelectric materials have excellent CMOS compatibility and polarization even in ultrathin films, which is regarded as promising candidate material for memory devices and related electronic devices. However, as the ferroelectric layer thickness scaling down, the consistency of device performance is inevitably affected by the complex polyphase and polycrystalline nature of HfO2-based ferroelectric thin films. Therefore, obtaining and controlling the texture of HfO2-based ferroelectric thin films is extremely important for regulating polarization orientation and improving ferroelectric polarization. In this work, 10 nm Hf0.5Zr0.5O2 (HZO) films were prepared by atomic layer deposition (ALD) on Nb-doped SrTiO3 (NSTO) single crystal substrates. The texture and orientation of HZO films were analyzed through the state-of-the-art spherical aberration corrected transmission electron microscope (Cs-TEM) technique. The domain matching epitaxy between HZO films and NSTO substrate helps eliminate lattice mismatch and residual misfit strain, and ultimately leads to the formation of <112> texture in HZO ferroelectric films. The obtained results represent lattice and interface play an extremely important role in regulating the ferroelectricity of HfO2-based films, which provides a way to design ultra-thin HfO2-based materials with excellent ferroelectric polarization by controlling the crystal structure and orientation.

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications

This paper presents the detailed analysis of n-channel Negative Capacitance Cylindrical Gate All Around Field Effect Transistor (NC-CGAAFET) of class Metal-Ferroelectric-Insulator Semiconductor (MFIS) at 2 nm technology node and its comparison with CGAAFET (Cylindrical Gate All Around Field Effect Transistor). NC-CGAAFET shows better performance in terms of ION, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), and ION/IOFF when compared to CGAAFET. Further, NC-CGAAFET is analyzed at different values of ferroelectric layer thickness (TFE), along with different values of spacer dielectric constant (K), spacer length (LSP) and nanowire diameter (DNW) and found that SS goes below Boltzmann's limit (60 mV/dec) and further decreases with increasing TFE. Also observed that Negative-DIBL increases as TFE increases. In addition to this, the device is optimized for NDR (Negative Differential Resistance) free operation, to be applicable for both analog and digital applications, by varying TFE. The optimized NDR free NC-CGAAFET offers SS of 59.33 mV/dec, DIBL of 13.91 mV/V, and the ION/IOFF ratio of 3.28x higher than conventional CGAAFET by operating at low power supply (VDD ∼ 0.65V).

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (tfe) has been systematically investigated. The proposed device yields higher values of on current, transconductance, cut off frequency, TFP, and Ion/Ioff ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers Ion, gm, fT, and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz V−1, respectively which are 220%, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the Ion/Ioff ratio for the proposed work is 8 × 1013 which is 7.1 × 103 times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to the improved RF/Analog and linearity performance, the presented device could be utilized for imminent next generation low power RFIC applications.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Performance assessment of dielectrically modulated negative capacitance germanium source vertical tunnel FET biosensor for detection of breast cancer cell lines

The paper presents a dielectrically modulated negative capacitance Germanium source vertical tunnel FET (DM-NC-Ge-vTFET) biosensor for detection of non-tumorigenic breast cell line (MCF-10A) and breast cancer cell lines of Hs578T, MDA-MB-231, MCF-7 and T47D. The proposed biosensor exploits the incorporation of ferroelectric (FE) layer with lateral and vertical band-to-band tunneling for improved detection sensitivity. The detecting strategy is determined by variations in the dielectric constant of various breast malignant cell lines. Sensitivity (Sn) is determined for both neutral and charged (positive/negative) biomolecules fordistinctive breast cell lines. Sn is determined by evaluating the shiftsin drain current. Sensitivity of 1.16 × 105 is attained for MCF-10A whereas Sn of 1.04 × 108 is realised for the T47D breast cell line for a completely filled nanogap. Additionally, the impact of FE layer thickness on the biosensor has been evaluated. It is observed that Sn of the proposed biosensor isenhanced for increase infill factor from partially to completely filled nanogap with a peak SNR value of approximately 61100. The biosensor’s selectivity and linearity have been evaluated. Lastly, the DM-NC-Ge-vTFET biosensor is benchmarked against existing published literatures andyields superior results in terms of its approximate sensitivity.

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

An Energy-Efficient Computing-in-Memory (CiM) cell design utilizing a Negative Capacitance (NC) FET has been proposed to support computing architectures for Deep Neural Networks (DNNs). The NCFET device characteristics for CiM architectures have been studied to determine an optimal device performance window by changing the thickness of ferroelectric layer (Tfe). The performance metrics such as read margin (RM), write margin (WM), read energy and write energy of NCFET 6 T SRAM cell are analyzed with varying Tfe at two different supply voltages 0.3 V and 0.5 V respectively. NCFET based SRAM cell design achieves higher RM and WM at Tfe of 3 nm and lower energy consumption at 1 nm Tfe as compared with the baseline SRAM cell design at both VDD = 0.3 V and VDD = 0.5 V respectively. 6 T NCFET based CiM cell design for performing basic input-weight product operation (IWP) has been demonstrated and performance comparison is done with baseline CMOS design at VDD = 0.3 V and VDD = 0.5 V. In comparison with the baseline CMOS CiM cell design, NCFET based SRAM CiM design achieves ∼2.59x and 1.62x lower energy consumption at VDD = 0.3 V and VDD = 0.5 V respectively with an optimal Tfe window of 1–3 nm.

Metal–Ferroelectric–Semiconductor Tunnel Junction: Essential Physics and Design Explorations

The essential physics of the ferroelectric tunnel junction (FTJ) is assessed with technology computer-aided design (TCAD) simulations and analytical models. With experimental data calibrations, a TCAD simulation framework including electrostatic potentials, ferroelectric (FE) polarizations, and nonlocal tunneling is built. Full regions of the FTJ operations, including the read/write, are then explored. Key parameters such as the memory state threshold voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {mth}}$ </tex-math></inline-formula> ) and the region boundary voltages are defined, and their model formulations are developed. With the essential physics captured, FTJ figure-of-merits (FoMs) are accessed with not only tunneling electroresistance (TER), but also power consumption. Design parameters from FE layer thickness, polarizations, and coercive field to silicon doping and metal work functions are studied, with their impacts on key FTJ FoMs evaluated.

Optimization of negative capacitance junctionless gate-all-around field-effect transistor using asymmetric non-local lateral Gaussian doping

Technology advancements directed towards Internet-of-Things (IoT) and wearable computing electronics applications are booming in low-power devices, which requires downscaling of power supply voltage without sacrificing the performance of the device. A negative capacitance junctionless gate-all-around field-effect transistor (NC-JL-GAAFET) is investigated using technology computer-aided design (TCAD) simulations to further suppress the short-channel effects and reduce power consumption. Lateral Gaussian doping (LGD), proposed for the NC-JL-GAAFET, is considered its main doping mode. An asymmetric structure with varying lengths of source/drain extension regions is introduced into non-local LGD NC-JL-GAAFET. The results reveal that the proposed device with a larger length ratio for drain extension region has a higher switching current ratio and lower subthreshold swing. Furthermore, the TCAD simulations validate that the electrical characteristics can be easily optimized by adjusting the ferroelectric (FE) layer thickness on the gate stack. Therefore, an asymmetric non-local LGD NC-JL-GAAFET provides a potential scaling solution for the next-generation low-power devices.

Random ferroelectric and dielectric phase distribution-induced device variation of negative capacitance field-effect transistors

Negative-capacitance field-effect transistors (NC-FETs) are significantly affected by their ferroelectric (FE)/dielectric (DE) phase configurations owing to the uncertainty of their crystalline phases. This study presents an analysis of random FE/DE grain distribution-induced variations from multiple perspectives using a seed random number generator in a technology computer-aided design (TCAD) simulation. The results obtained for the NC fully depleted silicon-on-insulator (NC-FDSOI) FETs indicate that device variations can be effectively reduced by increasing the probability of FE grains which improves the switching characteristics. Additionally, the FE distribution at the source presents a larger ON-state current (Ion), while the complete DE path from the source to the drain presents a larger OFF-state current (Ioff). The simulation results also demonstrate that reducing the lateral grain size reduces the device variations while improving the switching current ratio. Increasing the ferroelectric layer thickness of the NC-FDSOI FET can improve its switching performance; however, this also increases its variations. The random FE/DE distribution-induced variations can be reduced by adequately increasing the gate width through device scaling.

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ∼15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ∼3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ∼4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.

Dependence of RF/analog and linearity parameters on ferroelectric layer thickness in ferroelectric tunnel junction dual material double gate (FTJ-DMDG) TFET

In this article, we have proposed a ferroelectric tunnel junction (FTJ) dual material double gate (DMDG) TFET using TCAD simulator, where a ferroelectric (FE) layer is incorporated at tunnel junction to increase the band to band tunnelling rate. TCAD simulation result reflects that the inclusion of FE layer leads to improved ON current with enhanced BTBT rate as the thickness of FE layer (t FE) is reduced from 4 to 2 nm. The RF/analog parameter like transconductance (g m), gain (g m/g d), cut off frequency (f t), transconductance generation factor (TGP), gain frequency product (GFP), and transconductance frequency product (TFP) are improved by noticeable amount with down scaling in t FE value. The linearity analysis like g m2, g m3, voltage intercept points (VIP2 and VIP3), power intercept point (IIP3), and 1-dB compression point are also highlighted in FTJ-DMDG-TFET by varying t FE. A noticeable improvement in linearity behaviour is perceived with increased value in t FE.