Feed-forward Equalizer Research Articles

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology

This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed design technique, the power consumption, circuit complexity, and design cost are improved. The proposed RX with one-tap finite-impulse response (FIR) and second-tap IIR decision feedback equalizer (DFE) removes the FFE equalization in TX by moving the sampling point of main cursor in the received data. A simpler TX architecture with nMOS only output driver (NOD) owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) operation. The proposed transceiver was fabricated in a 65-nm CMOS technology. The RX achieves bit error rate (BER) less than 10^{-12} over a 22-dB channel loss at 32 Gb/s with 0.62-pJ/bit energy efficiency, and the TX with NOD has 0.77- and 0.40-pJ/bit energy efficiency at 32 Gb/s in differential mode and single-ended mode, respectively. The occupied area of TX and RX is 0.002 and 0.024 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance can attenuate reflection, and the PB-FFE compensates for increased insertion loss due to the damping resistor. In addition, the current flows only before and after a signal transition in the PB-FFE, improving energy efficiency and maintaining the turn-ON resistance during the no-transition region. A controller PHY based on this equalizer was fabricated in a 55-nm CMOS process. The PB-FFE increases the timing margin of the C/A signal from 0.23 to 0.29 UI at 1067 Mb/s. At 2133 Mb/s, the read timing and voltage margins of the DQ signal are 0.53 UI and 211 mV after read training, and its write margin is 0.72 UI and 230 mV, respectively, after write training.

Real-time reception of 106 Gbps PAM-4 transmission over an 80 km SSMF link enabled by CD pre-compensation.

In this study, we report, to the best of our knowledge, the first experimental demonstration of the real-time reception of a 106 Gbps PAM-4 transmission over an 80 km dispersion uncompensated standard single-mode fiber (SSMF) link. In the transmitter, a chromatic dispersion (CD) pre-compensation, aided by an optical IQ modulator, is implemented. The optimization guideline of driver signal amplitudes and bias voltages is proposed to enable optimal CD pre-compensation. In the receiver, a real-time PAM-4 module including simple feed-forward equalization (FFE) is used. After the transmission, the required optical signal-to-noise ratio (OSNR) at a bit error rate (BER) below 3.8 × 10-3 is determined to be 35 dB for 106 Gbps PAM-4 signals. The better BER of 6.9 × 10-4 is achieved successfully compared to the previously reported off-line reception. The demonstration confirms the feasibility of 80 km DCI based on CD pre-compensation under real-time reception.

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface

A duo-binary signaling has been applied to both transmitter and receiver for high-speed low-power DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this brief, because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme was applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V.

Enhanced hard decision based on multi-dimensional basis expansion in PAM4 transmission

Most of the PAM4 receivers eliminate the linear and nonlinear distortion by equalization and use independent symbols for decision. In this work, to remove the residual correlation between adjacent symbols after equalization, the enhanced hard decision (HD) based on multi-dimensional basis expansion is theoretically investigated and experimentally demonstrated for a 10-GHz directly modulated laser (DML) based 50-Gb/s PAM4 system. After 30-km standard single-mode fiber (SSMF) transmission, compared to the traditional HD, HD with 2-dimensional basis expansion (2D-HD) can achieve reliable transmission below the HD forward error correction (FEC) threshold with a linear feed-forward equalizer (FFE). Sensitivity gain of 1 dB and 2.2 dB can be further obtained by HD with 3-dimensional basis expansion (3D-HD) and 5-dimensional basis expansion (5D-HD), respectively. Moreover, even after the optimal Volterra nonlinear equalizer (VNLE), 5D-HD can still reduce the received optical power (ROP) by 0.6 dB.

Signal recovery based on optoelectronic reservoir computing for high speed optical fiber communication system

Signal recovery effects of a channel equalization method based on optoelectronic reservoir computing (RC) are investigated for actual high speed optical fiber communication systems. The RC is implemented numerically by using a Mach–Zehnder intensity modulator with an optoelectronic delay feedback loop. Two optical communication systems with different transmission distances and receivers based on 25G-class optics are built in-lab. 50-Gb/s non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) signals transmitted by the two systems are recovered by using optoelectronic RC and different combinations of feed-forward equalizer (FFE) with decision feedback equalizer (DFE) and maximum likelihood sequence estimation (MLSE), respectively. Under the same conditions, optoelectronic RC is better than FFE&DFE, and far superior to FFE&MLSE in the equalization performances. When the receiver is a positive–intrinsic–negative or avalanche photodiode, for the NRZ signal, compared with 45-tap FFE and 9-tap DFE, the sensitivity is increased by ∼3.2/3.4 dB; for the PAM4 signal, the sensitivity is improved by ∼4.9/4.6 dB compared with 123-tap FFE and 9-tap DFE. These experimental results show that the optoelectronic RC has excellent performances for signal recovery of different modulation formats and transmission systems.

Joint Equalization of Linear and Nonlinear Impairments for PAM4 Short-Reach Direct Detection Systems

Various neural network (NN)-based equalizers have been proposed as effective digital signal processing (DSP) tools for short-reach optical direct detection (DD) communication systems. However, they are mainly designed for solving nonlinear problems due to the intrinsic nonlinear activation function. In this letter, we propose novel DSP schemes to deal with both linear and nonlinear impairments in short-reach DD optical links, including cascade feedforward NN (FNN)/cascade recurrent NN (RNN)-based equalizers, and combination of feedforward equalization (FFE) and traditional non-cascade FNN/RNN-based equalizers. A 50-Gb/s pulse amplitude modulation (PAM)-4 directly modulated laser (DML)-based system is experimentally carried out and the bit-error-rate (BER) performance of the proposed DSP algorithms are compared. Experimental results show that cascade FNN/RNN and FNN/RNN-FFE could help improve the BER performance compared with traditional non-cascade FNN/RNN, since linear impairments are taken into account by either FFE or the cascade structure. With the help of the joint optimization of both linear and nonlinear effects through the network training process, cascade FNN/RNN shows great superiority over other DSP schemes. We also investigate on the impact of decision feedback equalization (DFE) concatenated with FNN/RNN. Compared with using FNN/RNN followed by FFE, no significant BER improvement can be found using DFE in place of FFE.

Net 220 Gbps/λ IM/DD Transmssion in O-Band and C-Band With Silicon Photonic Traveling-Wave MZM

We present the design and characterization of O-band and C-band silicon photonic (SiP) traveling wave Mach-Zehnder modulators (TW-MZM) allowing 220 Gbps/λ net rate operation. The designed modulators show over 45 GHz 3-dB E-O bandwidth with a single-segment design. In the O-band, with simple linear feed forward equalization, we transmit net 203 (200) Gbps signal over 2 km (10 km) of single-mode fiber (SMF) below the hard-decision forward error correction (HD-FEC) BER threshold of 3.8 × 10−3. With the aid of nonlinear Volterra equalizer and one 2.3Vpp driving signal, we transmit net 225 (216) Gbps PAM8 signals assuming 20% overhead soft-decision FEC with a normalized general mutual information (NGMI) threshold of 0.8798 over 2 km (10 km) of SMF. The C-band design enables net 220 Gbps in B2B and net 215 Gbps over 500 m of SMF above the specified NGMI threshold. These results are the highest reported net rate for SiP MZM in an intensity modulation direct-detection (IM/DD) system, fabricated entirely in a commercial foundry.

A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI

With increasing modulation order, a larger number of parallel source-series-terminated (SST) segments are required to implement precise feedforward equalization (FFE) tap-weight control in SST transmitters (TX). Due to the data routing complexity of the segmented structure, the dynamic power consumption of SST TX has become much more significant causing degradation in energy efficiency. This article presents a 32-Gb/s quarter-rate four-level pulse-amplitude modulation (PAM-4) SST TX with four-tap FFE implemented in 28-nm FDSOI CMOS technology using a high-impedance driver technique to decrease the gate loading of the data path of the SST TX. The output of the whole TX is kept matched to the standard characteristic impedance of the system even though the output impedance of the SST driver alone is high. The high-impedance driver technique decreases the total power consumption by 20% compared to the conventional design by providing a significant reduction in the capacitive load. Our measurement results show that the prototype TX consumes 77.9 mW and achieves an energy efficiency of 2.4 pJ/bit at a 32-Gb/s data rate for PAM-4 signaling.

Comparison of single-lane 100 Gb/s PAM-4 and DB-PAM-4 signals transmission based on 12G receiver with FFE and LDPC

Using low-bandwidth receivers to transmit single-wavelength 100 Gb/s data provides a low-cost and high-rate solution for the next generation passive optical networks (PONs). In this paper, we experimentally investigate the transmission of single-wavelength 100 Gb/s four-level pulse–amplitude modulation (PAM-4) and duobinary PAM-4 (DB-PAM-4) signal with a cost-effective 12 GHz PIN receiver. Feed-forward equalization (FFE) in conjunction with low-density parity-check (LDPC) is applied to enhance the bit error rate (BER) performance of the 25-km standard single-mode fiber (SSMF) transmitted signal. The Max-Log-maximum a posteriori (MAP) algorithm is utilized to computing soft information and provide it to LDPC decoding. As a result, under the same limited-bandwidth transmission conditions, DB-PAM-4 shows superior performance compared to PAM-4, reducing BER below the LDPC threshold 10−2. Error-free 25 km-transmission of 100 Gb/s DB-PAM-4 signal is realized employing 35-tap FFE and LDPC. On the contrast, the BER of PAM-4 cannot even be lower than 10−1, even with more taps and longer training sequences.

A new approach for designing and implementing ADF equalization for 5G frequency selective channel based on two operating phases of LS and RLS algorithms

In this paper, a new approach is proposed for implementing an adaptive decision feedback equalizer (ADFE) for the 5G channel. The proposed equalizer works in two phases. In the first phase, a least-squares (LS) algorithm with a variable-length training sequence is used to estimate the coefficients of the channel and the equalizer. In the second phase, the recursive least-squares algorithm estimates the channel and adapts the equalizer, jointly. According to the channel quality, a variable-length training sequence is used to estimate the channel vector and the coefficients of the equalizer. The feed-forward equalizer (FFE) compensates the effects of the transmitting filter and the channel filter. No matched filter is used in the receiver. The noise samples at the input of the proposed FFE are independent. The noise enhancement of the proposed FFE is less than the noise enhancement of its corresponding one in the conventional ADFE. The overall filtering response (OFR) from the input of the transmitting filter to the output of the FFE is calculated and used to estimate the coefficients of the feedback equalizer (FBE). The channel model, the FFE coefficients, the OFR vector, and the FBE coefficients are continuously updated every symbol period. Using a variable training sequence increases the bandwidth efficiency of the transmitted signal. Simulation results and real-time implementation measurements show that the convergence time and the steady-state error at the output of the proposed equalizer are smaller than their corresponding values in the conventional ADFE.

A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS

We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver's ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW.

2ch × 53-Gbps Optical Transmission Performance of a Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-μm LD Array-on-Si

This article presents a 2-channel 4-level pulse amplitude modulation (PAM4) transmitter front-end consisting of a 2-channel PAM4 shunt laser diode (LD) driver and flip-chip-bonded 1.3-μm LD array-on-Si that has the highest power efficiency yet reported for PAM4 transmitter front-ends. The driver was designed and fabricated using 65-nm CMOS technology, and the LD array-on-Si was fabricated using 1.3-μm membrane LD array-on-Si technology. To decrease the power consumption, the front-end does not use a high-speed digital-to-analog converter (DAC) or linear driver for generating the PAM4 signals. Instead, to generate clear PAM4 signals, the shunt LD driver incorporates DAC, and equalizing functions. The driver was designed with a photonic-electronic conversion system in SPICE, and the transmitter front-end was implemented with flip-chip-bonding interconnection between the driver and LD array-on-Si. The resulting 2-channel PAM4 transmitter front-end has high power efficiency. Our experiments show that in simultaneous operation, each channel could transmit 53-Gbps PAM4 signals, resulting in a power efficiency of 0.57 mW/Gbps. They also show that feed-forward equalization (FFE) with only 10 taps is enough for 2-km-long standard single-mode fiber (SSMF) transmission of 53-Gbps PAM4 signals with a bit error rate (BER) below 2.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> when the two channels are operated simultaneously.

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver with a three-point ZQ calibration scheme. This improves PAM-4 linearity by allowing the driver to compensate for its impedance variation caused by the change in the drain-source voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> ) to suit the four output levels considering both the TX and the receiver (RX). Resistors and inductors are eliminated from the voltage-mode (VM) driver, reducing the area requirement. The two-tap asymmetric feed-forward equalization (FFE) allocates six different coefficients to each minimum pull-up and pull-down transition, compensating for nonlinear equalization strengths and asymmetric characteristics of the driver. A prototype chip fabricated in the 65-nm CMOS has an area of 0.0333 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 0.64 pJ/bit. It achieves a data rate of 28 Gb/s/pin with a ratio level separation mismatch (RLM) of 0.993.

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology

This article describes the design of a 32 Gb/s four-level pulse amplitude modulation (PAM- 4) optical transceiver in a 40 nm CMOS technology. At the transmitter side, the laser driver is composed of an asymmetric waveform equalizer, a 3-tap feed-forward equalizer (FFE), and a novel active-back termination (ABT) circuit. The ABT circuit provides a self-tracking, tunable source impedance to match the characteristic impedance of different laser diodes. At the receiver side, the fully integrated optical receiver consists of a transimpedance amplifier (TIA), a variable gain amplifier (VGA), an automatic threshold tracking circuit (ATC), and a quarter-rate decision feedback equalizer (DFE). By using the adaptive ATC, it reduces the BER induced by the harmonic distortion along the signal path by more than 27X under a THD of −20dB. Both the ATC and DFE are automatically adapted by an on-chip sign-sign LMS (SSLMS) engine. Fabricated in TSMC 40 nm CMOS process, the chip area for the transmitter and receiver are about 0.029 mm2 and 0.23 mm2. The power consumptions are about 146.8 mW and 128.8 mW respectively for the PAM-4 transmitter and receiver.

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and low-frequency equalization (LF-EQ) is proposed to improve the BER performance and overall energy efficiency. The LF-EQ of the MP-CTLE eliminates the need for many DFE taps in SR/VSR applications to save power and area. A 1-tap feedforward equalizer (FFE) is used to further compensate for the high-frequency loss. We also use a ring oscillator based wide bandwidth phase-locked loop (WBW-PLL) as the multiphase clock generator (MPCG) in the clock and data recovery loop to save power with acceptable phase accuracy. Fabricated in 40-nm CMOS technology, the prototype receiver chip achieves error-free operation up to 52 Gb/s PAM-4 with superior bit efficiency of 0.126pJ/bit/s/dB while compensating 7.3-dB channel loss at 13GHz. With the proposed single-stage MP-CTLE, the receiver extends the error-free operation from PRBS-7 to PRBS-9. The BER bathtub curve at $10^{-6}$ is improved from 0.018 UI to around 0.1 UI.

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a two-stage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10−12, and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-digital-converter (ADC) in the RX AFE has an embedded 2-tap analog feed-forward equalizer. The design objective is to optimize the energy efficiency for the target data rate and the moderate-loss channel. For this purpose, the optimum modulation order that has the least ISI sensitivity for the given equalization capability is decided with a modeling study. All the equalization is performed in the analog domain to avoid the circuit complexity and power consumption disadvantages of the digital equalization in the selected high-order modulation. Thanks to the spectral efficiency of PAM-16 and the analog-only equalization, the figure-of-merit is improved significantly. Post-layout simulations show that the TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 32 Gb/s with PAM-16, which corresponds to 2.38 pJ/bit for the whole system.

Reduced-state MLSE for an IM/DD system using PAM modulation.

The performance of a high-speed intensity-modulation (IM)/direct-detection (DD) transmission system could be limited by the bandwidth of optical transceivers. One popular way to cope with this performance limitation is to utilize the maximum likelihood sequence estimation (MLSE) at the receiver. However, a practical problem of MLSE is its high implementation complexity. Even though the channel impulse response can be truncated by using a two-tap filter before applying the MLSE, it still faces an implementation problem when used for multi-level modulation formats. In this paper, we propose and demonstrate a reduced-state MLSE for band-limited IM/DD transmission systems using M-ary pulse amplitude modulation (PAM-M) formats. We use a conventional Viterbi algorithm to search a reduced-state trellis, which is constructed by using the coarse pre-decision of the signal equalized by a feed-forward equalizer. Thus, the proposed MLSE reduces the implementation complexity significantly. We evaluate the performance of the proposed reduced-state MLSE over 100∼140-Gb/s PAM-4/6/8 transmission systems implemented by using a 1.3-µm directly modulated laser. The results show that the proposed MLSE achieves almost the same performance as the conventional MLSE but reduces the implementation complexity by a factor of 4∼10 when the complexity is assessed by the number of multiplications and additions.