A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Chen Cai,Yong Chen,Danyu Wu,Dechao Lu,Jin Wu,Jian Luan,Xuqiang Zheng,Lei Zhou,Xinyu Liu

doi:10.3390/electronics10161873

Abstract

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Highlights

As the data centers rapidly evolve to accommodate higher information transfer rates, a high-speed serial interface has become the main candidate to deliver data transmission [1,2,3,4,5,6,7]
While an feed-forward equalizer (FFE) is embedded in a current-mode logic (CML) output driver, the output impedance and the swing can be adjusted by the termination resistor and the bias current, respectively
The data rate can be altered to multi-rate flexibly, e.g., if the data transfer rate needs to be DR = 16 Gb/s, and the local clock generate by phase-locked loop (PLL) is locked to f CK = 8 GHz, the dividers are set to DIV1 and DIV5, respectively; the final TXOUT is at 16 Gb/s, as desired

Summary

Introduction

As the data centers rapidly evolve to accommodate higher information transfer rates, a high-speed serial interface has become the main candidate to deliver data transmission [1,2,3,4,5,6,7]. The bandwidth requirements of those protocols keep increasing, and the decreased unit interval (UI) period becomes a bottleneck in high-speed transmitter (TX) design, which makes the timing budget extremely tight. The bandwidth-limited channel attenuates the high-frequency gain of the transmitted data due to the skin effect and dielectric loss [12,13,14,15], resulting in inter-symbol interference. To apply a wide operating range and multiple protocols, a high-operating range PLL is designed to generate the multi-frequency differential clocks, and the multi-rate TX lanes are proposed, in which the signal frequency of the multi-phase clocks can be configured according to the expected data rate. The optimized combiner with the 3-tap FFE is proposed to reduce the high-frequency channel loss.

Top Architecture

Multi-Rate TX Lane Implementation

Multi-Rate Lane Timing

Conclusions