2ch × 53-Gbps Optical Transmission Performance of a Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-μm LD Array-on-Si

Abstract

This article presents a 2-channel 4-level pulse amplitude modulation (PAM4) transmitter front-end consisting of a 2-channel PAM4 shunt laser diode (LD) driver and flip-chip-bonded 1.3-μm LD array-on-Si that has the highest power efficiency yet reported for PAM4 transmitter front-ends. The driver was designed and fabricated using 65-nm CMOS technology, and the LD array-on-Si was fabricated using 1.3-μm membrane LD array-on-Si technology. To decrease the power consumption, the front-end does not use a high-speed digital-to-analog converter (DAC) or linear driver for generating the PAM4 signals. Instead, to generate clear PAM4 signals, the shunt LD driver incorporates DAC, and equalizing functions. The driver was designed with a photonic-electronic conversion system in SPICE, and the transmitter front-end was implemented with flip-chip-bonding interconnection between the driver and LD array-on-Si. The resulting 2-channel PAM4 transmitter front-end has high power efficiency. Our experiments show that in simultaneous operation, each channel could transmit 53-Gbps PAM4 signals, resulting in a power efficiency of 0.57 mW/Gbps. They also show that feed-forward equalization (FFE) with only 10 taps is enough for 2-km-long standard single-mode fiber (SSMF) transmission of 53-Gbps PAM4 signals with a bit error rate (BER) below 2.3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> when the two channels are operated simultaneously.