A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer

Abstract

A controller PHY for high-capacity DRAM is presented. To reduce precursor and postcursor intersymbol interference due to its dispersive channel characteristics and a heavy load of many DRAM chips and to attenuate reflection on a highly reflective command/address (C/A) channel, a damping-resistor-aided three-tap pulse-based feed-forward equalizer (PB-FFE) is introduced. An appropriate damping resistance can attenuate reflection, and the PB-FFE compensates for increased insertion loss due to the damping resistor. In addition, the current flows only before and after a signal transition in the PB-FFE, improving energy efficiency and maintaining the turn-ON resistance during the no-transition region. A controller PHY based on this equalizer was fabricated in a 55-nm CMOS process. The PB-FFE increases the timing margin of the C/A signal from 0.23 to 0.29 UI at 1067 Mb/s. At 2133 Mb/s, the read timing and voltage margins of the DQ signal are 0.53 UI and 211 mV after read training, and its write margin is 0.72 UI and 230 mV, respectively, after write training.