Abstract
Near-threshold computing brings several times of magnitude improvement in energy efficiency of digital circuits. However, it also introduces several times of deteriorated delay variations caused by process, voltage, and temperature (PVT) variations. In situ timing monitoring-based adaptive techniques can mitigate excessive timing margins caused by PVT variations, but current frequency and/or voltage tuning methods cause large performance loss. In this paper, we propose a low overhead timing error prediction monitor and a super-fast clock stretching circuit to solve this problem. They are both optimized for near-threshold voltage of 0.5 V. When there are timing margins, the frequency will be increased. Until when the timing is intense due to variations, timing monitors will generate a predicted alarm signal. Accordingly, the system clock will be stretched immediately to avoid real timing errors. Applied on a 40-nm CMOS Bitcoin Miner chip, simulation results show that the whole system operating at near-threshold voltage can increase the frequency to up to $2.1\times $ compared with the original non-monitored circuit. Our method can increase the energy efficiency to mitigate near-threshold variations effectively.
Highlights
Near-threshold (NT) computing is very promising in integrated circuit design, in that it brings several times of magnitude improvement in energy efficiency [1], [2]
To mitigate this over-pessimistic timing margin waste problem, many adaptive techniques based on in-situ timing monitoring had been proposed [3]–[11], [17]–[21], such as RazorII [3], Razor-lite [4], double-sampling with time-borrowing (DSTB) [5], iRazor [6], HEPP [8] and so on
Since the best energy efficiency point locates at the near-threshold voltage region for digital circuits [1], it becomes necessary for a timing monitor to be able to work reliably at near-threshold voltage (NTV) which is a challenge
Summary
To mitigate this over-pessimistic timing margin waste problem, many adaptive techniques based on in-situ timing monitoring had been proposed [3]–[11], [17]–[21], such as RazorII [3], Razor-lite [4], DSTB [5], iRazor [6], HEPP [8] and so on They monitored the circuit timing during runtime, and used adaptive voltage scaling (AVS) to decrease power consumption, or adaptive frequency scaling (AFS) to increase working frequency as much as possible. Since the best energy efficiency point locates at the near-threshold voltage region for digital circuits [1], it becomes necessary for a timing monitor to be able to work reliably at near-threshold voltage (NTV) which is a challenge Another big issue is that, in these in-situ timing monitoring systems, once there is a timing error/warning, they usually need to decrease the frequency immediately to avoid further errors. Applied on a Bitcoin Miner chip, system simulation results show that it can increase the frequency to up to 210% compared to the nonmonitoring system working at signoff frequency
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