A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging

Abstract

This paper presents an adaptive and resilient domino register file design featuring in-situ timing margin and error detection for the performance-critical domino read path. Voltage/frequency is adapted for slow-changing variations such as low-frequency supply noise, temperature fluctuation, and aging-induced degradation. Dynamic adaptation is combined with error detection and recovery for fast voltage droops and random data access patterns in the presence of within-die process variations. Throughput and energy efficiency gains are higher than the replica/canary based critical path approach. Timing margin is tracked by double-sampling the read output and its delayed version at the same clock edge. Timing errors are detected by double-sampling and comparing the read output within a clock window. The sensing errors in the precharge/evaluate domino read path are converted into timing errors using a conditional delayed-bitline precharge technique that does not impact the subsequent precharge operation. The proposed techniques incur 6–13% area overhead and 0.2–0.3% power overhead for a 4 Kb sub-array. The measurement results from a 22 nm tri-gate CMOS testchip demonstrate 21% throughput and 67% energy efficiency improvement with a peak energy efficiency of 409 GOPS/W.